Multilayer Power Interconnect for Semiconductor IC Voltage Drop
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor integrated circuits, the miniaturization has led to increased power consumption and resistance in interconnects, making it difficult to supply power with low resistance and reduce power supply voltage drop, especially with multilayering not effectively addressed in existing technologies.
Innovation Solution
A semiconductor integrated circuit device configuration with a multilayered interconnect system where the first power supply interconnect extends in the same direction as the IO cell row, and a second power supply interconnect extends perpendicular to it, along with interconnect pieces at both ends of the power supply IO cell, to reduce resistance and voltage drop while avoiding design rule errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power supply interconnect is formed in a single layer, then device complexity is reduced, but resistance increases and power supply voltage drop cannot be effectively reduced
Solution Approach 1:
The patent transitions from a single-layer power supply interconnect to a multilayer interconnect structure. The first power supply interconnect is formed in a first interconnect layer, and a second power supply interconnect is formed in a second interconnect layer, utilizing the vertical dimension to reduce resistance and power supply voltage drop without significantly increasing overall device complexity.
2Reliability
If the first power supply interconnect extends through the power supply IO cell area, then power supply continuity is maintained, but interconnect design rule errors occur
Solution Approach 1:
The patent segments the power supply interconnect into two separate layers. The first power supply interconnect in the first layer does not extend through the power supply IO cell area, avoiding design rule errors. The second power supply interconnect in the second layer provides the necessary power supply continuity through the power supply IO cell area, thus maintaining reliability while ensuring design rule compliance.
3Loss of energy
If interconnect layers are increased to reduce resistance, then power supply voltage drop is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by forming the first power supply interconnect in the first layer primarily in signal IO cell areas, and forming the second power supply interconnect in the second layer primarily in power supply IO cell areas. This localized approach reduces resistance where needed while simplifying the manufacturing process by avoiding the need to form complex multilayer interconnect structures throughout the entire device.
Data Source
AI summary
For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.