Multi-Layer Power Module Substrate for Higher Density and Isolation
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Solution Overview
Problem
Conventional Intelligent Power Modules (IPMs) using Direct Bonded Copper (DBC) or Insulated Metal Substrate (IMS) substrates are limited by the use of a single copper layer, which restricts design flexibility and thermal performance, particularly in creating complex circuit patterns and enhancing power density.
Innovation Solution
A multi-layer substrate structure is introduced, featuring a first insulation layer between bottom and top metal layers, with exposed portions covered by a second insulation layer and conductive traces, allowing for the integration of semiconductor dies and passive devices, and utilizing a Thermally Conductive Isolated Layer (TCIL) to enhance thermal conductivity and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single copper layer is used in DBC or IMS substrates, then the fabrication process is simple, but the design flexibility and power density are limited
Solution Approach 1:
The patent transitions from a single-layer copper structure to a multi-layer copper structure by adding vertical dimensionality. Multiple copper layers are stacked with insulation layers in between, enabling complex 3D circuit patterns while maintaining fabrication feasibility through sequential layer processing
Solution Approach 2:
The substrate structure combines multiple materials including copper layers, ceramic insulation layers, and epoxy resin to create a composite multi-layer structure. This composite approach enables both electrical conductivity and electrical isolation while improving power density and thermal management
2Power
If a single copper layer is used, then the manufacturing process is straightforward, but thermal performance and power density are restricted
Solution Approach 1:
Multiple copper layers are stacked vertically to increase the effective conductive cross-section area, thereby increasing power density. The vertical stacking allows more current paths without increasing the planar footprint, directly addressing the power density limitation
Solution Approach 2:
The circuit pattern is segmented across multiple layers with insulation layers separating them. This segmentation allows independent routing of different signal paths, enabling complex circuit designs while maintaining manufacturing feasibility through layer-by-layer fabrication
3Reliability
If the first insulation layer is fully covered, then electrical isolation is improved, but thermal conductivity is reduced
Solution Approach 1:
The insulation layer is selectively applied only where electrical isolation is required, rather than uniformly covering the entire substrate. This local application allows heat to conduct through exposed ceramic regions while maintaining electrical isolation in covered areas, optimizing both electrical and thermal performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer substrate design enables higher power density and improved thermal management, supporting complex circuit patterns while maintaining electrical isolation, suitable for high-voltage applications with reduced package size.
Implementation Method 1
The second insulation layer isolates the first conductive traces from the second conductive traces
Implementation Method 2
The multi-layer substrate design enables higher power density and improved thermal management
Data Source
AI summary
An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.