Multilayer Power Module Layout for Low-Inductance Fast Switching
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Solution Overview
Problem
Conventional power modules suffer from parasitic impedances, particularly loop inductance, which cause voltage overshoot, ringing, increased switching losses, and EMI, limiting the maximum switching frequency and stability of power semiconductor devices.
Innovation Solution
A power module design with a custom layout featuring terraced power terminals and laminated buss bars to minimize loop inductance, ensuring equalized current paths and low inductance connections between power devices, allowing for high current and voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power module designs are used, then power devices can be contained and electrically connected, but parasitic loop inductance causes voltage overshoot, ringing, increased switching losses, and EMI
Solution Approach 1:
The patent transitions from planar two-dimensional current paths to three-dimensional stacked current paths by arranging power devices and terminals in multiple vertical layers. This dimensional change allows current loops to be folded back on themselves in the vertical dimension, significantly reducing loop inductance and eliminating voltage overshoot and ringing while improving stability.
Solution Approach 2:
The patent implements nested current paths where return currents are positioned directly beneath forward currents in stacked layers, creating concentric nested loops. This nesting minimizes the enclosed area of current loops, reducing parasitic inductance and preventing voltage overshoot and ringing harmful effects.
2Loss of energy
If conventional power module designs are used, then power devices can be connected, but loop inductance increases switching losses
Solution Approach 1:
By stacking power devices and terminals in multiple vertical layers, the patent creates short three-dimensional current paths that minimize loop inductance. This dimensional approach reduces the area enclosed by current loops, directly lowering switching losses while managing the harmful effect of loop inductance.
Solution Approach 2:
The patent positions return current paths directly beneath forward current paths, allowing the magnetic fields generated by opposing currents to cancel each other out. This converts the potentially harmful inductive effects into beneficial field cancellation, reducing switching losses.
3Productivity
If conventional power module designs are used, then power devices can be connected, but maximum switching frequency is limited due to parasitic impedances
Solution Approach 1:
The stacked three-dimensional architecture creates short current paths with minimal loop inductance, removing the parasitic impedance bottleneck that limited switching frequency. This dimensional change enables high-frequency switching while maintaining stability through controlled impedance paths.
Solution Approach 2:
The patent fundamentally changes the geometric parameters of current paths by transitioning from planar to stacked configurations. This parameter change reduces loop area and inductance, enabling higher switching frequencies while maintaining system stability.
Data Source
AI summary
The disclosure is directed to a power module that includes at least one power substrate, a housing arranged on the at least one power substrate, and a first terminal electrically connected to the at least one power substrate. The first terminal includes a contact surface located above the housing at a first elevation. The power module includes a second terminal including a contact surface located above the housing at a second elevation different from the first elevation, a third terminal electrically connected to the at least one power substrate, and a plurality of power devices electrically connected to the at least one power substrate.