Low Inductance Multilayer Power Module with Pin Fin Cooling
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Solution Overview
Problem
Current power modules face challenges with increased heat generation and parasitic impedances, such as loop inductance, which limit their efficiency, stability, and switching frequency, especially when using advanced power semiconductor devices like Gallium Nitride (GaN) and Silicon Carbide (SiC), leading to higher switching losses and Electromagnetic Interference (EMI).
Innovation Solution
A power module design with a low inductance structure, featuring a multilayer internal conductor layout, terraced power terminals, and pin fins for direct cooling, which optimizes current distribution and reduces parasitic impedances, allowing for faster switching and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional power module structures are used, then manufacturing and assembly are simpler, but loop inductance is higher causing voltage overshoot and ringing
Solution Approach 1:
The patent transitions from conventional two-dimensional PCB-style layouts to a three-dimensional multilayer power module architecture. Multiple copper layers are stacked vertically with power and ground planes alternating, creating short current paths through vertical vias. This dimensional change reduces loop inductance by minimizing the area enclosed by current loops while maintaining structural integrity and thermal performance.
Solution Approach 2:
The patent implements nested current paths where inner copper layers are surrounded by outer layers, creating concentric current loops. The current flows through multiple nested layers from inner to outer or vice versa, with each layer contributing to flux cancellation. This nesting arrangement reduces effective inductance by creating opposing magnetic fields that cancel each other, thereby improving stability without excessive structural complexity.
2Productivity
If switching frequency is increased to reduce external filter size, then power density improves, but parasitic impedances cause higher switching losses and EMI
Solution Approach 1:
The patent changes the electrical parameters of the module by optimizing copper layer thickness, trace widths, and via dimensions to minimize parasitic resistance and inductance. The multilayer structure with optimized spacing between power and ground planes reduces loop inductance, allowing higher switching frequencies with reduced switching losses. This parameter optimization enables the module to operate efficiently at high frequencies without excessive EMI or energy loss.
3Power
If advanced power semiconductors like GaN and SiC are used, then power density and efficiency improve, but heat generation increases beyond operational limits
Solution Approach 1:
The patent incorporates a liquid cooling system with cooling channels formed in the base plate or heat sink structure. Coolant flows through these channels to directly remove heat from the power semiconductor devices. This hydraulic cooling approach efficiently manages the high heat generation from advanced semiconductors like GaN and SiC, maintaining operational temperatures within safe limits while enabling high power density operation.
4Reliability
If loop inductance is reduced to minimize voltage overshoot, then stability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the current path into multiple discrete segments across different copper layers, connected by vias. Each layer and via can be manufactured and positioned independently with standard tolerances. This segmentation allows the overall low-inductance structure to be achieved through cumulative effect of multiple segments rather than requiring single-piece high-precision manufacturing. The modular nature of multilayer construction facilitates assembly with conventional precision equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables higher power density, reduced switching losses, increased stability, and lower EMI, facilitating the full utilization of advanced power semiconductors and improving overall system performance.
Implementation Method 1
a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module
Data Source
AI summary
A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.