Multi-Layer Power Module Substrate for Higher Power Density
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Solution Overview
Problem
Conventional Intelligent Power Modules (IPMs) using DBC or IMS substrates are limited to a single layer of copper, restricting design flexibility and thermal performance, which hinders the development of higher power density and more complex circuit patterns.
Innovation Solution
A multi-layer substrate structure is introduced, featuring a first insulation layer between metal layers with exposed portions and a second insulation layer that isolates conductive traces, allowing for additional conductive traces on top, along with a Thermally Conductive Isolated Layer (TCIL) made of epoxy and ceramic fillers to enhance thermal conductivity and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single layer of copper is used in DBC or IMS substrates, then the fabrication process is simple, but the design flexibility and thermal performance are limited
Solution Approach 1:
The patent transitions from a single-layer copper structure to a multi-layer copper structure by adding vertical dimensionality. Multiple copper layers are stacked with insulation layers in between, allowing complex circuit patterns to be formed on different planes. This dimensional expansion enables sophisticated power module designs while maintaining compatibility with conventional fabrication processes.
Solution Approach 2:
The copper structure is segmented into multiple discrete layers separated by insulation layers. Each copper layer can be independently patterned and optimized for specific functions, such as power distribution, signal routing, or thermal management. This segmentation allows for enhanced design flexibility and thermal performance without fundamentally changing the fabrication approach.
2Device complexity
If a single layer of copper is used in DBC or IMS substrates, then the structure is simple, but the power density is restricted
Solution Approach 1:
By stacking multiple copper layers vertically, the patent increases the effective copper volume within the same footprint area. This vertical stacking enables higher current carrying capacity and improved thermal conduction paths, directly enhancing power density while maintaining a compact overall structure.
Solution Approach 2:
The patent creates a composite structure combining multiple copper layers with insulation layers (such as ceramic or epoxy-based materials). This composite architecture provides both electrical conduction pathways through the copper layers and thermal management capabilities through the insulating materials, enabling high power density with effective heat dissipation.
3Adaptability or versatility
If more complex circuit patterns are desired, then design flexibility must increase, but the fabrication process becomes more difficult
Solution Approach 1:
Complex circuit patterns are achieved by utilizing multiple vertical layers instead of attempting to create all patterns on a single plane. Each layer can contain simplified patterns that, when combined across layers, form complex three-dimensional circuit architectures. This approach maintains fabrication simplicity while enabling design complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer substrate design enables higher power density and more complex circuit patterns while maintaining thermal performance, suitable for high-voltage applications with reduced package size and using conventional manufacturing equipment.
Implementation Method 1
The second insulation layer isolates the first conductive traces from the second conductive traces
Implementation Method 2
The DBC substrate provides good isolation by virtue of a ceramic layer and good thermal performance owing to the thermal conductivity of the ceramic layer
Data Source
AI summary
An example semiconductor package comprises a multi-layer substrate having a bottom metal layer, a top metal layer, and a first insulation layer between bottom metal layer and the top metal layer. A plurality of first conductive traces are formed in the top metal layer. A second insulation layer is disposed over the exposed portions of the first insulation layer and over segments of the first conductive traces. A plurality of second conductive traces formed on top of the second insulation layer. One or more semiconductor dies are mounted on the one or more second segments of the conductive traces. One or more bond wires couple the semiconductor dies to one or more of the second conductive traces. A mold compound covers at least a portion of the semiconductor dies, the second insulation layer, the first conductive traces, and the second conductive traces.