Multilayer Power Terminal Structure for Low-Inductance Semiconductor Modules
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Solution Overview
Problem
Conventional power semiconductor elements experience surge voltages due to parasitic inductance in main circuit wires, which can cause damage and limit the efficiency and reliability of the devices.
Innovation Solution
A semiconductor device configuration featuring an insulated circuit substrate with a conductive plate, semiconductor chips, and external connection terminals comprising an inner-side conductor layer, insulating layer, and outer-side conductor layer, which reduces parasitic inductance through eddy currents generated by magnetic fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional main circuit wires are used, then the device structure is simple, but parasitic inductance increases causing surge voltages
Solution Approach 1:
The external connection terminal is divided into multiple conductor layers (first conductor layer, second conductor layer, third conductor layer) stacked in the thickness direction, with insulating layers between them. This segmentation reduces parasitic inductance by creating multiple current paths and reducing the loop area, thereby suppressing surge voltages while maintaining structural integrity.
Solution Approach 2:
The patent transitions from a planar single-layer conductor structure to a three-dimensional multi-layer stacked structure. By utilizing the thickness direction (z-axis) to stack conductor layers, the invention reduces the effective loop area for eddy currents and parasitic inductance, achieving lower surge voltages without increasing the footprint area.
2Reliability
If multi-layer conductor structure is used, then parasitic inductance decreases, but manufacturing complexity increases
Solution Approach 1:
The multi-layer conductor structure is designed with conductor layers nested within each other in the thickness direction, separated by insulating layers. This nested configuration allows the terminal to be formed as an integrated stack that can be manufactured using standard multi-layer PCB or metalization techniques, reducing the impact of manufacturing complexity while achieving parasitic inductance reduction.
3Reliability
If conductor layers are closely stacked, then parasitic inductance reduces, but insulation requirements increase
Solution Approach 1:
Insulating layers are introduced as intermediary elements between the first, second, and third conductor layers. These insulating layers provide electrical isolation while allowing the conductor layers to be closely stacked in the thickness direction, thereby reducing parasitic inductance without compromising insulation strength. The insulating layers act as mediators that enable close spacing while maintaining electrical safety.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively suppresses induced voltages during switching operations, reducing parasitic inductance in the external connection terminals and the entire conversion circuit unit, thereby enhancing the reliability and efficiency of the semiconductor device.
Implementation Method 1
an outer-side conductor layer provided at a circumference of the inner-side conductor layer... an eddy current is caused inside the metal plate because of a magnetic field generated by the power terminal
Implementation Method 2
an eddy current is caused in both of a pair of metal plates in a direction opposite to the recovery current due to an electromagnetic induction effect
Data Source
AI summary
A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.