Multilayer Power Wiring Capacitor for Voltage Stability

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Solution Overview

Problem

Existing semiconductor integrated circuits face challenges in stabilizing power supply voltage at low voltage and high speed operations due to localized power consumption, leading to operation errors and signal jitters, with existing solutions either increasing manufacturing cost or failing to provide sufficient capacitance.

Innovation Solution

A semiconductor integrated circuit with a multilayer wiring structure where the top and next-to-top metal wiring layers cross each other, with insulating film in between, forming capacitors that provide sufficient power supply capacitance without complicating the manufacturing process or increasing costs, by exclusively using these layers for power supply wirings and not mixing them with signal wirings.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power supply wiring and ground wiring are thickened to decrease resistance, then power supply voltage stability is improved, but wiring layer complexity and manufacturing cost increase

Engineering Contradiction:
Improvepower supply voltage stabilityVSAvoidwiring layer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent transitions from planar wiring expansion to three-dimensional capacitor structure formation. By utilizing the vertical dimension between wiring layers MTOP and MTOP-1 to form capacitors with insulating film 5, the invention provides additional power supply stabilization capability without increasing wiring layer complexity or manufacturing cost.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If capacitor is formed between power supply and ground to stabilize power supply voltage, then power supply stability is improved, but manufacturing cost and process complexity increase

Engineering Contradiction:
Improvepower supply voltage stabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the capacitor formation process with the existing wiring layer manufacturing process. The insulating film 5 is formed as part of the interlayer insulation structure between MTOP and MTOP-1, and capacitors are created by defining conductive regions within this film using standard photolithography and etching techniques, thereby integrating capacitor fabrication into the conventional wiring manufacturing flow without adding separate manufacturing steps.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If capacitor is formed in same layer between VDD and VSS wirings, then manufacturing process is simplified, but sufficient electrode area and capacitance cannot be secured

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidpower supply capacitance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent resolves the electrode area limitation by moving from two-dimensional planar capacitor formation within a single layer to three-dimensional capacitor formation utilizing the vertical space between wiring layers MTOP and MTOP-1. This dimensional transition allows capacitors to achieve sufficient capacitance values while maintaining manufacturing simplicity through integration with the existing multilayer wiring structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively stabilizes power supply voltage and prevents signal jitter by securing a large capacitance per unit area, maintaining operational stability without increasing manufacturing complexity or costs.

Implementation Method 1

a top layer insulating film disposed between there... forming capacitors that provide sufficient power supply capacitance

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

an insulating material having a relatively high dielectric constant is formed thinly between these two wiring layers

Methodology Applied
Scientific EffectDielectric: Dielectric

Data Source

PatentUS7659629B2Semiconductor integrated circuit
Publication Date: 2010.02.09 KAWASAKI MICROELECTRONICS
  • US7659629B2 patent drawing
  • US7659629B2 patent drawing
  • US7659629B2 patent drawing

AI summary

A semiconductor integrated circuit having a multilayer wiring structure is provided which includes: a top metal wiring layer (MTOP) including a plurality of top layer power supply wirings and a next-to-top metal wiring layer (MTOP-1) directly below the top metal wiring layer MTOP including a plurality of next-to-top layer power supply wirings. Each of the top layer and the next-to-top layer power supply wirings also includes first potential wirings for supplying a first potential to the circuit elements and second potential wirings for supplying a second potential to the circuit elements. The top layer power supply wirings and the next-to-top layer power supply wirings cross each other and have a top layer insulating film disposed between them. First and second contacts are provided in the insulating film for connecting the first potential wirings and second potential wirings in the top and the next-to-top metal wiring layers with each other.