Multilayer Processing Mask for Semiconductor Etching

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Solution Overview

Problem

Conventional semiconductor manufacturing methods face challenges in forming fine resist patterns with high accuracy and maintaining pattern fidelity during dry etching, leading to issues like pattern collapse, line edge roughness, and deformation, especially in dual damascene processes.

Innovation Solution

A manufacturing method involving a multilayer film process where a processing mask layer is formed with hardening treatment, comprising a lower organic film and a middle layer, which are then etched using a resist pattern as a mask, allowing for precise control of etching resistance and pattern retention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If the film thickness of the resist is reduced to prevent pattern collapse, then pattern stability is improved, but etching resistance deteriorates causing film chipping and increased LER

Engineering Contradiction:
Improvepattern stabilityVSAvoidetching resistance
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent divides the processing mask into multiple layers: a lower organic film layer (150-300 nm thick) providing etching resistance, a middle layer (80 nm thick) controlling reflection, and an upper resist layer (250 nm thick) forming the pattern. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between pattern stability and etching resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a composite multilayer structure combining different materials with distinct properties: the lower organic film provides high etching resistance, the middle layer controls optical reflection, and the upper resist provides pattern definition. This composite approach allows simultaneous optimization of etching resistance and pattern stability without compromise.

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If the film thickness of the resist is reduced to improve resolution, then manufacturing precision is improved, but pattern stability deteriorates causing pattern collapse

Engineering Contradiction:
ImproveresolutionVSAvoidpattern stability
Core Design Contradiction:
Manufacturing precisionVSStability of the object's composition

Solution Approach 1:

The patent separates the resolution function (handled by the upper resist layer with optimized thickness and lithographic properties) from the stability function (handled by the lower organic film and middle layer providing structural support and etching resistance). This segmentation allows thin resist for high resolution while maintaining overall pattern stability through the multilayer support structure.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a monolayer resist is used to simplify the process, then device complexity is reduced, but both pattern stability and etching resistance cannot be satisfied simultaneously

Engineering Contradiction:
Improveprocess complexityVSAvoidpattern formation accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies segmentation by dividing the mask structure into three functional layers, each optimized for its specific role. This resolves the contradiction by showing that while complexity increases, the manufacturing precision and pattern stability improve significantly, making the additional complexity necessary and justified.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite materials with different properties in each layer: the lower organic film for etching resistance, the middle layer for reflection control, and the upper resist for pattern definition. This composite structure enables simultaneous satisfaction of multiple requirements that a single material cannot achieve.

Inventive Principle:
Principle #40Composite materials

4Reliability

If hardening treatment is applied to enhance etching resistance, then reliability is improved, but pattern deformation occurs due to structural changes in the resist

Engineering Contradiction:
Improveetching resistanceVSAvoidpattern fidelity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the hardening function from the pattern formation function by applying hardening treatment specifically to the lower organic film layer, while keeping the upper resist layer untreated to maintain pattern fidelity. This selective segmentation allows etching resistance enhancement without pattern deformation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies hardening treatment locally to the lower organic film layer where etching resistance is needed, while leaving the upper resist layer with its original properties for accurate pattern formation. This local differentiation resolves the contradiction between etching resistance and pattern fidelity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces pattern roughness and maintains fidelity to the original design, improving etching resistance and accuracy in semiconductor device manufacturing, particularly in dual damascene structures.

Implementation Method 1

heat hardening treatment

Methodology Applied
Scientific EffectHeat hardening: Heat Treatment

Implementation Method 2

plasma dry etching

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS8092703B2Manufacturing method of semiconductor device
Publication Date: 2012.01.10 RENESAS ELECTRONICS CORP
  • US8092703B2 patent drawing
  • US8092703B2 patent drawing
  • US8092703B2 patent drawing

AI summary

It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.