Multilayer Redistribution Structure Assembly to Reduce RDL Warpage
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Solution Overview
Problem
The mismatch in coefficient of thermal expansion between materials used in the multilayer redistribution layer (RDL) and temporary carrier boards leads to warpage issues during the fabrication of semiconductor substrate structures, affecting yield and electrical performance.
Innovation Solution
The semiconductor substrate structure is fabricated by forming multiple groups of circuit structures on separate temporary carrier boards, which are then directly assembled into a multilayer redistribution structure, reducing warpage and improving yield and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple layers are continuously formed on a temporary carrier board, then a multilayer redistribution structure is achieved, but warpage increases due to CTE mismatch between materials
Solution Approach 1:
The patent divides the multilayer redistribution structure into multiple separate groups of circuit structures, each fabricated independently on its own temporary carrier board. These segmented structures are then assembled together through bonding of conductive connectors. This segmentation reduces the cumulative CTE mismatch stress within any single fabrication process, thereby reducing warpage while still achieving the desired multilayer complexity.
2Device complexity
If multiple layers are continuously formed on a temporary carrier board, then a multilayer redistribution structure is achieved, but yield and electrical performance deteriorate due to warpage
Solution Approach 1:
By segmenting the fabrication into multiple independent groups that are assembled rather than continuously formed, the patent reduces warpage-induced defects and electrical performance degradation, thereby improving yield and reliability while maintaining multilayer complexity.
Solution Approach 2:
The patent performs preliminary fabrication of circuit structures on separate temporary carrier boards before final assembly. This preliminary action allows each group to be optimized and stabilized independently, reducing the risk of warpage-related failures in the final multilayer structure and improving overall yield and electrical performance.
3Stability of the object's composition
If circuit structures are fabricated separately and assembled, then warpage is reduced, but manufacturing process complexity increases
Solution Approach 1:
While segmentation into multiple fabrication groups increases process steps, it enables parallel processing and modular manufacturing. Each group can be fabricated independently and then assembled through standardized bonding processes, which manages the complexity through modularity rather than eliminating it entirely.
Data Source
AI summary
A semiconductor substrate structure including a first group of circuit structure, a second group of circuit structure, and a first device is provided. The first group of circuit structure includes multiple first wiring layers and multiple first conductive connectors, and each of the first conductive connectors includes a conductive cap. The second group of circuit structure includes multiple second wiring layers and multiple second conductive connectors. The first group of circuit structure and the second group of circuit structure are electrically connected through bonding of the first conductive connectors and the second conductive connectors to form a multilayer redistribution structure. The first device is disposed on the first group of circuit structure and electrically connected to portion of the first conductive connectors or the first device is disposed on the second group of circuit structure and electrically connected to portion of the second conductive connectors. A semiconductor structure and manufacturing method thereof are also provided.