DRAM Memory Cell With Multilayer Read Transistor for Multi-Bit Storage
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Solution Overview
Problem
Existing DRAM cells made of IGZO material face difficulties in achieving multi-bit information storage through a single storage node.
Innovation Solution
A memory cell design with a read transistor comprising multiple channel layers made of different materials, allowing for different current ranges under varying voltage conditions, enabling multi-bit information storage by controlling conductivity through the gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single storage node is used in DRAM cell made of IGZO material, then the device structure is simple, but multi-bit information storage cannot be achieved
Solution Approach 1:
The read transistor channel is segmented into multiple channel layers with different materials (first channel layer, second channel layer, third channel layer), each contributing differently to current flow. This segmentation enables multi-bit information storage by controlling which layers conduct current under different voltage conditions, achieving versatility without proportionally increasing overall device complexity.
Solution Approach 2:
The patent employs composite material structure in the read transistor channel by combining multiple channel layers made of different materials. Each layer has distinct electrical properties that allow selective conduction based on applied voltage, enabling the storage node to represent multiple bit states (1-bit, 2-bit, or 3-bit storage) while maintaining a relatively compact device structure.
2Measurement precision
If small current values are produced in read transistor, then power consumption is low, but peripheral circuit detection becomes difficult
Solution Approach 1:
The read transistor exhibits dynamic current response based on applied voltage thresholds. By adjusting gate voltage levels, the transistor can operate in different conduction modes where higher currents are produced during read operations to improve detection precision, while lower currents are maintained during standby to reduce power consumption. The multi-layer channel structure enables this dynamic behavior through selective layer activation.
3Productivity
If storage capacitance is reduced for high-density memory, then memory density increases, but charge leakage becomes more significant
Solution Approach 1:
The patent utilizes parameter changes in the multi-layer channel structure to control charge retention. By carefully designing the thickness, material composition, and electrical properties of each channel layer, the system achieves optimal balance between capacitance and leakage. The different materials in each layer provide distinct band structures and carrier mobilities that can be tuned to minimize leakage while maintaining sufficient capacitance for high-density memory operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables large current values for better peripheral circuit detection, increased storage capacitance, reduced charge leakage, and lower refresh frequency, facilitating high-density and high-performance memory operations.
Implementation Method 1
controlling conductivity through the gate electrode
Implementation Method 2
a main working principle is to represent a binary bit as 1 or 0 by using an amount of charges stored in a capacitor
Data Source
AI summary
A memory cell of a dynamic random access memory, an array, a memory, and a device are provided. The memory cell includes a write word line, a write bit line, a write transistor, a read word line, a read bit line and a read transistor. The read transistor includes multiple channel layers composed of different materials. A gate electrode, a first electrode and a second electrode of the write transistor are connected to the write word line, the write bit line and a gate electrode of the read transistor respectively. The first and second electrodes of the write transistor are respectively source and drain electrodes of the write transistor. First and second electrodes of the read transistor are connected to the read bit line and the read word line respectively. The first and second electrodes of the read transistor are respectively source and drain electrodes of the read transistor.