Multilayer Resist Structure for Semiconductor Wiring
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Solution Overview
Problem
Current methods fail to effectively suppress the evolution of poisoning gas in semiconductor device manufacturing, leading to resolution failures in wiring patterns during the dual damascene process, especially when using high-density plasma for forming SiO2 or Si3N4 layers, which also results in incomplete filling of via holes with the SOC layer.
Innovation Solution
A multilayer resist structure comprising an SOC layer, a high-density SiO2 layer, and a chemically amplification type resist is formed in order, with the SiO2 layer acting as a block layer to prevent gas evolution and the SOC layer ensuring via hole filling, while the SOG layer is used to protect the SOC layer from plasma etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-density plasma is used for forming SiO2 or Si3N4 layers, then manufacturing precision is improved, but poisoning gas evolution increases causing resolution failures in wiring patterns
Solution Approach 1:
An SOC layer is introduced as an intermediary between the SiO2/Si3N4 layer and the via holes. This SOC layer acts as a barrier that prevents poisoning gas generated during high-density plasma processing from reaching and damaging the wiring pattern, while still allowing the plasma process to form the insulating layer with high precision
Solution Approach 2:
The SOC layer is formed in advance before the high-density plasma process. This preliminary action ensures that the via holes are already filled with the SOC material, creating a protective barrier that prevents poisoning gas evolution during subsequent plasma processing steps
2Productivity
If process temperature is reduced to arrange BEOL devices in wiring layer, then device integration is improved, but poisoning gas evolution increases through via holes
Solution Approach 1:
The SOC layer serves as a mediator that blocks poisoning gas from evolving through via holes, enabling low-temperature processing conditions required for high device integration without suffering from gas evolution problems
3Adaptability or versatility
If via holes are opened on upper electrode for BEOL device formation, then device functionality is improved, but poisoning gas evolves increasingly in dual damascene process
Solution Approach 1:
The SOC layer is deposited to fill via holes opened for BEOL device formation, creating a protective barrier that prevents poisoning gas evolution during subsequent dual damascene processing while maintaining the via hole structure needed for device connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses poisoning gas evolution and improves the yield of functional elements like solid electrolyte switches by ensuring precise wiring patterns and complete via hole filling, enhancing the reliability of semiconductor devices.
Implementation Method 1
a chemically amplification type resist is formed
Implementation Method 2
when using high-density plasma for forming SiO2 or Si3N4 layers
Data Source
AI summary
The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multi-layered copper interconnect on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.