Multi-Layer Impedance Matching for Compact >10 GHz RF Interconnects
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Solution Overview
Problem
Existing electronic devices face challenges in providing satisfactory impedance matching for millimeter and centimeter wave communications without consuming excessive space, particularly at frequencies above 10 GHz.
Innovation Solution
The implementation of multi-layer impedance matching structures within a dielectric substrate, including varying via pads and conductive vias, coupled with a signal trace and ground traces, to perform impedance matching between a signal conductor and radio-frequency components, such as antennas, while minimizing space occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional impedance matching structures are used at frequencies above 10 GHz, then impedance matching performance can be achieved, but the space occupied in the device becomes excessive
Solution Approach 1:
The patent transitions from planar two-dimensional impedance matching structures to three-dimensional multi-layer structures embedded within a dielectric substrate. By stacking multiple conductive layers and via pads vertically, the design achieves effective impedance matching at frequencies above 10 GHz while reducing the horizontal footprint area occupied by the structure.
Solution Approach 2:
The impedance matching structure is nested within the dielectric substrate, with multiple conductive layers and via pads embedded inside the substrate volume. This nested configuration allows the impedance matching functionality to be integrated into the existing substrate structure, minimizing additional space requirements while maintaining performance at millimeter-wave frequencies.
2Area of stationary object
If the area of via pads is reduced to minimize space, then device compactness is improved, but impedance matching capability at high frequencies deteriorates
Solution Approach 1:
Instead of increasing via pad area in the horizontal plane, the patent compensates by adding vertical dimensionality through multiple stacked conductive layers and via pads. This multi-layer configuration provides additional degrees of freedom for impedance control, allowing small individual via pads to achieve effective impedance matching when combined in a three-dimensional arrangement.
Solution Approach 2:
The patent employs a composite structure combining multiple conductive materials and dielectric materials in stacked layers. The via pads are formed as part of a multi-material assembly where conductive vias penetrate through dielectric layers, creating a composite impedance matching structure that achieves high-frequency performance with minimized individual component areas.
3Area of stationary object
If multi-layer impedance matching structures are implemented, then space efficiency is improved, but device complexity increases
Solution Approach 1:
The patent merges the impedance matching function with the existing substrate structure by embedding the multi-layer conductive elements directly into the dielectric substrate. Rather than adding separate impedance matching components, the design integrates these elements into the substrate fabrication process, reducing overall device complexity despite the multi-layer configuration.
Data Source
AI summary
An electronic device may include a transmission line path having a signal conductor embedded in a substrate. A contact pad may be patterned on a surface of the substrate. A radio-frequency component may be mounted to the contact pad using solder. Multi-layer impedance matching structures may couple the signal conductor to the contact pad. The matching structures may include a set of via pads and a set of conductive vias coupled in series between the signal conductor and the contact pad. The area of the via pads may vary across the set of via pads and/or the aspect ratio of the conductive vias may vary across the set of conductive vias. The matching structures may perform impedance matching between the signal conductor and the radio-frequency component at frequencies greater than 10 GHz while occupying a minimal amount of space in the device.