Multi-Layer Ring Oscillator for Digital Circuit Power Regulation

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Solution Overview

Problem

Existing power consumption regulation techniques in digital circuitry, such as single-layer ring oscillators, are inadequate in compensating for fabrication anomalies and variations in propagation delay, leading to inefficiencies in maintaining target performance and power consumption.

Innovation Solution

A multi-layer ring oscillator is employed, with interconnects fabricated on different layers, allowing for adjustable supply voltage and clocking frequency adjustments to compensate for anomalies in propagation delay, ensuring target performance and power consumption across layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-layer ring oscillator is used for power consumption regulation, then the device complexity is reduced, but the manufacturing precision and reliability deteriorate due to inadequate compensation for fabrication anomalies and propagation delay variations

Engineering Contradiction:
Improveoscillator structure complexityVSAvoidpropagation delay compensation accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent transitions from a single-layer ring oscillator to a multi-layer ring oscillator structure. By adding the vertical dimension (multiple layers) to the oscillator design, the system can compensate for fabrication anomalies and propagation delay variations that cannot be addressed in a single planar layer, thereby improving manufacturing precision without significantly increasing overall device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The ring oscillator is segmented across multiple layers, with different stages or components of the oscillator distributed on separate layers. This segmentation allows independent optimization and compensation of propagation delays in different layers, improving the overall precision of delay matching while maintaining manageable complexity through modular structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If supply voltage and clocking frequency are dynamically adjusted to maintain target performance, then the reliability is improved, but the device complexity increases due to additional regulation circuitry

Engineering Contradiction:
Improveperformance consistencyVSAvoidregulation circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The multi-layer ring oscillator structure inherently provides self-compensation for propagation delay variations through its layered architecture. The oscillator automatically adjusts its operation across layers to maintain target performance, reducing the need for external regulation circuitry and thereby limiting the increase in device complexity while still improving reliability.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system employs feedback mechanisms where the actual propagation delay is measured and compared against target values, and supply voltage or clocking frequency is adjusted based on the error signal. This feedback loop maintains performance consistency while the multi-layer structure reduces the magnitude of adjustments needed, moderating the complexity of the regulation circuitry.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8324974B1Regulating power consumption of digital circuitry using a multi-layer ring oscillator
Publication Date: 2012.12.04 WESTERN DIGITAL TECHNOLOGIES INC
  • US8324974B1 patent drawing
  • US8324974B1 patent drawing
  • US8324974B1 patent drawing

AI summary

A computing device is disclosed comprising digital circuitry fabricated on a multi-layer integrated circuit including a first layer and a second layer, and a multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer. The propagation delay frequency is compared to a reference frequency to generate a frequency error, and at least one of a supply voltage and a clocking frequency applied to the digital circuitry is adjusted in response to the frequency error.