Multi-Layer Source/Drain Epitaxy for Semiconductor Resistance Reduction
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased source/drain resistance and contact resistance, which hinder device performance and integration density.
Innovation Solution
The formation of source/drain regions with decreased resistance is achieved through epitaxial growth of multiple layers, including a high dopant out-diffusion layer, a buffer layer, and a high-strain layer, with specific thickness and dopant concentration profiles, and germanium concentrations to reduce overlap, source/drain, and channel resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but source/drain resistance and contact resistance increase
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain structure where each layer has different material composition and doping concentration optimized for its specific function. The first layer (SiGe) provides strain enhancement, the second layer (Si) serves as a buffer, and the third layer (SiGe with higher Ge concentration) provides additional strain and low resistance, with each layer locally optimized to address the resistance problem while maintaining compatibility with scaled dimensions
Solution Approach 2:
The patent employs composite materials by combining multiple semiconductor layers with different compositions (SiGe, Si, and SiGe with varying germanium concentrations) to form the source/drain region. This composite structure leverages the advantageous properties of each material: SiGe for strain-induced mobility enhancement, pure Si as a lattice-matched buffer, and high-Ge SiGe for low resistance and additional strain, collectively solving the resistance increase problem in scaled devices
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but device performance deteriorates due to increased resistance
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain structure where each layer has different material composition and doping concentration optimized for its specific function. The first layer (SiGe) provides strain enhancement, the second layer (Si) serves as a buffer, and the third layer (SiGe with higher Ge concentration) provides additional strain and low resistance, with each layer locally optimized to address the resistance problem while maintaining compatibility with scaled dimensions
Solution Approach 2:
The patent employs composite materials by combining multiple semiconductor layers with different compositions (SiGe, Si, and SiGe with varying germanium concentrations) to form the source/drain region. This composite structure leverages the advantageous properties of each material: SiGe for strain-induced mobility enhancement, pure Si as a lattice-matched buffer, and high-Ge SiGe for low resistance and additional strain, collectively solving the resistance increase problem in scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases overall resistance and improves device performance by optimizing the structure and composition of source/drain regions, enhancing integration density and device speed.
Implementation Method 1
epitaxially growing a first semiconductor material having a first thickness in the first recess, the first semiconductor material being silicon; epitaxially growing a second semiconductor material having a second thickness over the first semiconductor material
Implementation Method 2
A material having high dopant out-diffusion may be used for the first source/drain layer, which may decrease overlap resistance (Rov)
Implementation Method 3
A material having low resistivity and exerting high strain may be used for the third source/drain layer, which may decrease source/drain resistance (Rsd), contact resistance (Rcsd), and channel resistance (Rch)
Data Source
AI summary
A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess; and forming a source/drain region in the first recess, forming the source/drain region including epitaxially growing a first semiconductor material in the first recess, the first semiconductor material being silicon; epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium; and epitaxially growing a third semiconductor material over the second semiconductor material, and the third semiconductor material having a germanium concentration from 60 to 80 atomic percent, the third semiconductor material having a germanium concentration greater than the germanium concentration of the second semiconductor material.