Multilayer Semiconductor Measurement Using Dynamic Condition Adjustment

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Solution Overview

Problem

Existing methods for measuring pattern dimensions on semiconductor integrated circuits, particularly multilayered circuit elements, are inefficient due to the complexity of setting numerous length measurement points and fail to account for the layered structure, leading to inadequate evaluation of semiconductor device fabrication processes.

Innovation Solution

A method and apparatus that dynamically adjust measurement conditions based on the workpiece image and semiconductor circuit element state, allowing for improved measurement efficiency by performing length measurements between multiple layers using design data, enabling objective evaluation of upper-level and lower-level layer performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If numerous length measurement points are set for multilayered circuit elements, then measurement precision is improved, but device complexity and measurement time increase

Engineering Contradiction:
Improvelength measurement precisionVSAvoidmeasurement system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the measurement process into layer-specific measurement points for each semiconductor layer. Instead of treating all measurement points uniformly across the entire circuit element, the system divides measurement tasks by layer, allowing targeted measurement at critical interfaces between layers. This segmentation reduces the complexity of managing numerous measurement points while maintaining precision at each layer level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to measurements by measuring not only within individual layers but also across layer interfaces. The measurement system now operates in three dimensions by capturing both in-plane measurements within layers and vertical measurements at layer boundaries, enabling comprehensive evaluation of multilayered structure without proportionally increasing measurement point complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If measurement points are distributed across multiple layers, then measurement coverage is improved, but measurement time increases

Engineering Contradiction:
Improvefabrication process evaluation accuracyVSAvoidmeasurement time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary identification and classification of measurement points by layer before actual measurement begins. The system pre-organizes measurement points into layer-specific groups and establishes the measurement sequence in advance, allowing the measurement system to efficiently navigate and measure points across multiple layers without time-consuming on-the-fly decisions during data collection.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent ensures continuous measurement action by establishing an efficient measurement sequence that flows smoothly through layer interfaces. The system maintains continuous data collection without unnecessary interruptions or repetitions when moving between layers, ensuring that each measurement point is visited exactly once in the optimal sequence, thereby minimizing total measurement time while maintaining comprehensive coverage.

Inventive Principle:
Principle #20Continuity of useful action

3Ease of operation

If traditional 2D measurement methods are used, then measurement simplicity is maintained, but ability to evaluate multilayered structure is insufficient

Engineering Contradiction:
Improvemeasurement operation simplicityVSAvoidmultilayered structure evaluation capability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal measurement framework that can handle both traditional 2D measurements within individual layers and new 3D measurements across layer interfaces. The same measurement system and software platform perform both functions, making the system adaptable to various measurement scenarios without requiring separate specialized equipment for different measurement types.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements a nested measurement structure where 2D measurement points within layers are nested within a broader 3D measurement framework that includes vertical layer interface measurements. The measurement system first handles traditional 2D measurements within each layer, then nests these results within a comprehensive 3D evaluation that adds layer-to-layer relationships, creating a hierarchical measurement approach that maintains simplicity while adding capability.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances measurement efficiency and accuracy for multilayered semiconductor circuit elements, providing a more comprehensive evaluation of semiconductor device performance and fabrication state.

Implementation Method 1

CD-SEM is an apparatus of the type which measures the size of a pattern formed on a workpiece based on secondary electrons obtained by scanning an electron beam on the workpiece of interest

Methodology Applied
Scientific EffectElectron beam scanning: Electron Beam

Implementation Method 2

a pattern image formed by CD-SEM or the like is compared with its CAD data to thereby detect a deformation amount of the pattern

Methodology Applied
Scientific EffectImage comparison and edge detection: Image Processing

Data Source

PatentUS8019161B2Method, device and computer program of length measurement
Publication Date: 2011.09.13 HITACHI HIGH TECH CORP
  • US8019161B2 patent drawing
  • US8019161B2 patent drawing
  • US8019161B2 patent drawing

AI summary

A workpiece size measurement method suitable for length measurement of multilayered circuit elements with increased complexities is disclosed. This method employs a technique for changing measurement conditions in a way pursuant to either an image of workpiece or the situation of a target semiconductor circuit element to be measured when measuring pattern sizes on the workpiece image using design data of the semiconductor circuit element. With such an arrangement, adequate measurement conditions are selectable in accordance with the state of workpiece image and/or the state of a circuit element formed on the workpiece, thereby making it possible to improve the measurement efficiency. A workpiece size measurement apparatus using the technique is also disclosed.