Multilayer Semiconductor Gettering Structure for Wafer Warpage Reduction
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Solution Overview
Problem
In semiconductor IC manufacturing, high leakage current due to fast diffusing impurities and defects in active device regions leads to poor yields, and existing extrinsic gettering methods like polysilicon layers cause wafer warpage and defect formation, such as silicon nodules, which can result in misprocessing and quality issues.
Innovation Solution
A multi-layer structure comprising amorphous semiconductor layers and polycrystalline semiconductor layers separated by non-conductive dielectric layers, formed in-situ within a single processing apparatus, which reduces warpage, provides extrinsic gettering, and minimizes defect formation without additional cleaning steps or wafer transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polycrystalline semiconductor layer is deposited on the back surface of a monocrystalline semiconductor wafer for extrinsic gettering, then impurity removal capability is improved, but the polycrystalline layer recrystallizes during high temperature processing and loses gettering capability
Solution Approach 1:
The invention divides the single polycrystalline gettering layer into multiple alternating layers of amorphous semiconductor material and dielectric material. This segmented structure prevents complete recrystallization during high temperature processing while maintaining distributed gettering sites throughout the multilayer structure, thereby preserving gettering capability throughout the processing sequence.
Solution Approach 2:
The invention creates a composite multilayer structure combining amorphous semiconductor layers with dielectric layers. The amorphous semiconductor provides gettering capability while the dielectric layers act as barriers that prevent grain growth and recrystallization. This composite approach maintains the beneficial properties of polycrystalline gettering while avoiding the harmful recrystallization effect.
2Reliability
If a polycrystalline semiconductor layer is deposited on the semiconductor wafer for extrinsic gettering, then impurity removal is improved, but wafer warpage occurs due to compressive stress
Solution Approach 1:
The invention segments the continuous polycrystalline layer into discrete amorphous semiconductor layers separated by dielectric layers. This segmentation distributes the stress across multiple thin layers rather than concentrating it in a single thick layer, reducing the overall compressive stress on the wafer and minimizing warpage while maintaining gettering function.
Solution Approach 2:
The invention changes the physical state of the semiconductor material from polycrystalline to amorphous in the deposited layers. Amorphous semiconductor material exhibits different stress characteristics compared to polycrystalline material, and when combined with the alternating dielectric layers, this parameter change effectively reduces the net compressive stress on the wafer, thereby reducing warpage.
3Reliability
If a low temperature oxide backside sealing layer is used during epitaxial deposition, then wafer sealing is achieved, but silicon nodule defects form on the lower surface
Solution Approach 1:
The invention merges the backside sealing function with the extrinsic gettering function into a single integrated multilayer structure. The alternating amorphous semiconductor and dielectric layers simultaneously provide both sealing and distributed gettering capability, eliminating the need for separate LTO sealing layer and preventing nodule formation while maintaining effective backside protection.
Solution Approach 2:
The invention replaces the simple LTO sealing layer with a composite multilayer structure consisting of amorphous semiconductor layers and dielectric layers. This composite structure provides superior backside sealing while the amorphous semiconductor material prevents silicon nodule formation through its unique atomic structure that does not promote nodule growth during epitaxial processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layer structure effectively reduces wafer warpage and defect formation, maintains gettering capability, and improves thermal stability, leading to enhanced semiconductor device performance and yield while being cost-effective and efficient.
Implementation Method 1
The first amorphous semiconductor layers, the second amorphous semiconductor layers, and the third amorphous semiconductor layers compensate for excessive stress provided by the polycrystalline semiconductor layers to reduce warpage of the semiconductor wafer
Implementation Method 2
The presence of the polycrystalline layer induces stress on the semiconductor wafer, which acts to getter or remove the unwanted impurities during subsequent high temperature processing
Implementation Method 3
The first amorphous semiconductor layers, the second amorphous semiconductor layers, and the third amorphous semiconductor layers compensate for excessive stress provided by the polycrystalline semiconductor layers to reduce warpage of the semiconductor wafer
Data Source
AI summary
A method of forming a semiconductor device includes providing a semiconductor substrate and forming amorphous semiconductor layers adjacent a major surface of the substrate. The method includes interposing dielectric layers between the amorphous semiconductor layers. The method includes forming polycrystalline semiconductor layers adjacent the amorphous semiconductor layers. The method includes interposing dielectric layers between the polycrystalline semiconductor layers and between the last amorphous semiconductor layer and the first polycrystalline semiconductor layer. The method includes forming a fine-grain polycrystalline semiconductor layer adjacent the polycrystalline semiconductor layers but is separated from the last polycrystalline semiconductor layer by an additional dielectric layer. The fine-grain polycrystalline semiconductor layer is formed at a higher temperature than the polycrystalline semiconductor layers and the amorphous semiconductor layers. A semiconductor device can be formed in another major surface of the semiconductor substrate.