Multilayer Series Inductor Layout for High-Q RF Chips
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional planar inductors occupy large chip area and struggle to achieve high inductance value with high-Q factor on silicon wafers due to increased proximity effects and parasitic capacitance, making it difficult to fabricate efficient on-chip inductors for RF applications.
Innovation Solution
The use of multiple thick metal wiring structures connected in series across multiple wiring levels, forming a spiral inductor configuration where each level partially overlaps with the next, allowing for increased inductance density and reduced chip size, while maintaining a high Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional planar inductors are used, then they occupy large chip area, but they fail to achieve high inductance value with high-Q factor
Solution Approach 1:
The patent transitions from a two-dimensional planar inductor design to a three-dimensional multi-layer stacked configuration. Multiple inductor layers are positioned at different vertical levels (first layer, second layer, third layer) with selective overlapping, effectively utilizing the third dimension (z-axis) to increase inductance density without proportionally increasing chip area while maintaining high Q factor through optimized spatial arrangement that reduces parasitic effects
2Reliability
If the number of turns and width of inductor lines are increased to achieve high inductance value, then inductance increases, but proximity effects and parasitic capacitance increase causing Q factor to decrease
Solution Approach 1:
The inductor is segmented into multiple discrete layers (first layer, second layer, third layer) with controlled overlapping regions. This segmentation allows the magnetic flux to be distributed across multiple spatial levels, increasing effective inductance while the separated structures minimize proximity effects between adjacent conductors, thereby maintaining high Q factor
Solution Approach 2:
The patent employs a nested configuration where the second layer is positioned to overlap partially with both the first and third layers, creating a nested spatial arrangement. This nesting optimizes magnetic coupling between layers to enhance inductance while the controlled overlap geometry minimizes capacitive coupling, preserving energy storage efficiency and Q factor
3Area of stationary object
If multiple wiring levels are used to increase inductance density, then chip size is reduced, but manufacturing complexity increases
Solution Approach 1:
By utilizing vertical stacking of multiple wiring levels, the patent achieves high inductance density within a compact chip footprint. The third dimension provides additional space for inductor turns without increasing lateral chip dimensions, effectively decoupling inductance value from chip area while the modular layer structure manages manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of compact, high-inductance, high-Q factor inductors, reducing chip size and production costs, and improving performance in RF applications by minimizing proximity effects and parasitic capacitance.
Implementation Method 1
An inductor is a passive two-terminal electrical component that stores energy in a magnetic field as electric current flows through its coils
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.