Multilayer Shield Structure for Transistor Parasitic Capacitance Reduction
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Solution Overview
Problem
Compact field effect transistor designs face challenges with increased electric coupling between gate and drain runners, leading to parasitic feedback capacitance that reduces amplifier stability and gain due to miniaturization requirements.
Innovation Solution
A multilayered shield structure is implemented between the input and output of the transistor, comprising forked structures in multiple conductive layers with electrically conductive vias, strategically located near tap locations to reduce electric coupling, including shield traces between gate and drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compact circuit design is implemented to miniaturize integrated circuits, then the quantity of IC dies per wafer increases and cost is reduced, but electric coupling between gate and drain runners increases leading to parasitic feedback capacitance
Solution Approach 1:
A shield structure comprising a first shield element and a second shield element is introduced as an intermediary between the gate runner and drain runner. The shield elements are positioned to block electric field coupling, with the first shield element adjacent to the gate runner and the second shield element adjacent to the drain runner, effectively reducing parasitic feedback capacitance while maintaining compact dimensions
Solution Approach 2:
The shield structure utilizes the vertical dimension by positioning shield elements at different heights above the substrate. The first shield element is positioned at a first height and the second shield element at a second height, creating a three-dimensional shielding arrangement that effectively blocks electric field coupling in the compact horizontal space
2Volume of moving object
If compact circuit design is implemented, then device size is reduced, but amplifier stability and gain are reduced due to increased electric coupling
Solution Approach 1:
The shield structure acts as an intermediary barrier between the gate and drain regions, blocking the harmful electric field coupling that would otherwise occur in compact designs. This allows the device to maintain small dimensions while preserving amplifier stability by preventing the parasitic feedback that causes oscillation
Solution Approach 2:
The shield structure converts the potentially harmful electric field coupling into a beneficial configuration by redirecting electric field lines. The shield elements are positioned to intercept and redirect the electric fields, transforming what would be harmful parasitic coupling into a controlled field distribution that maintains device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer shield structure effectively reduces feedback capacitance, enhancing amplifier gain without degrading stability and enabling a compact, highly integrated system design.
Implementation Method 1
A field effect transistor (FET) in such a high power semiconductor device package may include interdigitated drain and gate runners. The gate of the FET is driven by an input signal tapped from the gate runner. Miniaturization of integrated circuits is critical to enable compact circuit design, increase the quantity of IC dies per wafer, and thereby reduce the cost of such IC dies. However, compact circuit designs can increase electric coupling between, for example, the gate and drain runners of such integrated circuits. This electric coupling can add parasitic feedback capacitance that may reduce amplifier stability and reduce gain.
Data Source
AI summary
A transistor includes a semiconductor substrate having first and second terminals. An interconnect structure, on an upper surface of the substrate, is formed of layers of dielectric material and electrically conductive material. The conductive material includes a first pillar connected with the first terminal, a second pillar connected with the second terminal, and a shield system between the first and second pillars. The shield system includes forked structures formed in at least two conductive layers of the interconnect structure and at least partially surrounding segments of the second pillar. The shield system may additionally include shield traces formed in a first conductive layer positioned between gate fingers and the first pillars and/or the shield system may include shield runners that are located in an electrically conductive layer that is below a topmost electrically conductive layer with the first pillar being connected to a runner in the topmost conductive layer.