Multilayer Si Nanocrystal Memory for Retention and Write Speed
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face challenges in maintaining high-speed write/erase capabilities while improving memory retention, as reducing Si nanocrystal particle size increases energy barriers, leading to degradation in write/erase performance and reliability.
Innovation Solution
A nonvolatile semiconductor memory design featuring multiple nanoparticle layers with varying sizes, where a larger lower nanoparticle layer acts as a buffer to maintain low-voltage high-speed write/erase operations and enhance memory retention by controlling energy barriers, ensuring that the energy required for charging electrons in each layer differs significantly from thermal fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the particle size of Si nanocrystals is reduced to increase the energy barrier, then memory retention characteristics are improved, but write/erase performance degrades due to low energy barrier
Solution Approach 1:
The nanoparticle layer is divided into multiple layers with different particle sizes. The lower nanoparticle layer has larger particles that provide a lower energy barrier for fast write/erase operations, while the upper nanoparticle layer has smaller particles that provide a higher energy barrier for improved memory retention. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between retention and write/erase speed.
Solution Approach 2:
Different regions of the nanoparticle layer are given different local properties by varying the particle size in different layers. The lower layer uses larger particles optimized for write/erase operations, while the upper layer uses smaller particles optimized for retention. This local differentiation allows the system to simultaneously achieve both fast write/erase and high retention without compromise.
2Productivity
If the write/erase voltage is increased to eliminate the low energy barrier, then write/erase performance is maintained, but device reliability is lost
Solution Approach 1:
The write/erase function is segmented between two layers: the lower layer with larger particles handles the write/erase operations at low voltage due to its lower energy barrier, while the upper layer with smaller particles ensures retention reliability. This segmentation eliminates the need to increase voltage, thereby maintaining device reliability while achieving fast write/erase performance.
Solution Approach 2:
The lower nanoparticle layer with larger particles acts as an intermediary that facilitates low-voltage write/erase operations by providing a lower energy barrier pathway. This intermediary layer enables fast write/erase without requiring high voltage, thus protecting device reliability while maintaining productivity.
3Device complexity
If a single nanoparticle layer is used, then device structure is simple, but both memory retention and write/erase performance cannot be optimized simultaneously
Solution Approach 1:
The nanoparticle layer is segmented into multiple layers with different particle sizes to simultaneously optimize both memory retention and write/erase performance. The lower layer with larger particles optimizes write/erase speed, while the upper layer with smaller particles optimizes retention. This segmentation achieves dual optimization at the cost of increased structural complexity.
Solution Approach 2:
The nanoparticle layer is constructed as a composite structure with two distinct types of nanoparticles (different sizes) arranged in specific layers. This composite approach allows the system to combine the advantages of both large particles (fast write/erase) and small particles (high retention) within a single integrated structure, achieving optimized performance for both functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents degradation of write/erase performance, improves memory retention characteristics, and maintains low-voltage high-speed write/erase operations by utilizing a multilayered structure of Si nanocrystals in the tunnel insulating films with carefully controlled particle sizes, addressing the limitations of single-layer nanoparticle designs.
Implementation Method 1
an energy barrier ΔE by the Coulomb blockade effect and quantum confinement of the Si nanocrystals blocks the information charge tunnel
Implementation Method 2
an energy barrier ΔE by the Coulomb blockade effect and quantum confinement of the Si nanocrystals blocks the information charge tunnel
Implementation Method 3
using a tunnel current, charges are exchanged between an Si surface and the trap level in a silicon nitride film
Data Source
AI summary
According to one embodiment, in a nonvolatile semiconductor memory in which a charge store layer is formed on a tunnel insulating film formed on a channel region of a semiconductor substrate, a first nanoparticle layer containing first conductive nanoparticles is formed on the channel side, and a second nanoparticle layer containing a plurality of second conductive nanoparticles having an average particle size larger than the first conductive nanoparticles is formed on the charge store layer side. An average energy value ΔE1 required for charging one electron in the first conductive nanoparticle is smaller than an average energy value ΔE required for charging one electron in the second conductive nanoparticle, and a difference between ΔE1 and ΔE is larger than a heat fluctuation energy (kBT).