Multi-Layer SiGe Source/Drain Fabrication for Stress and Dislocation Control
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Solution Overview
Problem
The existing embedded SiGe technology in semiconductor fabrication faces challenges such as increased lattice mismatch and dislocations due to rising Ge content differences between the Si substrate and SiGe layer, leading to degraded device performance, poor cap layer uniformity, and poor metal silicide formation.
Innovation Solution
A method involving epitaxial growth of multiple SiGe layers with varying Ge content, including a first seed layer, a second layer with higher Ge content, and a third layer with lower Ge content, followed by a Si cap layer, to reduce dislocations and improve cap layer profile and metal silicide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ge content in SiGe layer is increased to apply compressive stress on channel, then hole mobility is improved, but lattice mismatch increases causing dislocation and device performance degradation
Solution Approach 1:
The SiGe layer is segmented into multiple layers with different Ge contents. The first SiGe layer has lower Ge content (reducing lattice mismatch with Si substrate), while the second SiGe layer has higher Ge content (providing sufficient compressive stress). This segmentation allows both low lattice mismatch and high stress to be achieved simultaneously.
Solution Approach 2:
Different regions of the SiGe structure have different Ge contents tailored to local requirements. The first SiGe layer near the substrate has lower Ge content to match the substrate lattice, while the second SiGe layer has higher Ge content to provide compressive stress. This local quality variation resolves the contradiction between lattice matching and stress application.
2Reliability
If SiGe epitaxial layer is grown higher than substrate surface in SRAM regions, then compressive stress is enhanced, but crystal plane forms on opposing sides causing poor cap layer uniformity
Solution Approach 1:
The SiGe structure is segmented into multiple layers with varying Ge contents. The first SiGe layer with lower Ge content has better lattice matching and promotes planar growth, preventing crystal plane formation on opposing sides. This allows the cap layer to grow uniformly while still providing sufficient compressive stress through the combined structure.
3Reliability
If Ge content in SiGe layer is increased to improve PMOS performance, then carrier mobility is enhanced, but metal silicide formation becomes difficult causing electric leakage and resistance issues
Solution Approach 1:
The SiGe structure is divided into layers with different Ge contents. The first SiGe layer has lower Ge content that allows good metal silicide formation, while the second SiGe layer has higher Ge content that provides carrier mobility enhancement. This segmentation enables both metal silicide formation and high carrier mobility to be achieved.
Solution Approach 2:
Different Ge content regions are created to satisfy different functional requirements. Regions requiring metal silicide formation have lower Ge content, while regions requiring high carrier mobility have higher Ge content. This local quality variation resolves the contradiction between metal silicide formation and carrier mobility enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases Ge content in SiGe source/drain regions, reduces dislocations, enhances cap layer uniformity, and facilitates the formation of metal silicide, thereby improving semiconductor device performance.
Implementation Method 1
epitaxial growing a first SiGe seed layer with a constant Ge content; epitaxial growing a second SiGe layer with a constant Ge content on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content on the second SiGe layer
Data Source
AI summary
A method of fabricating a semiconductor device is disclosed. The method includes the steps of forming recesses in a semiconductor substrate; epitaxial growing a first SiGe seed layer with constant Ge content in the recesses; epitaxial growing a second SiGe layer with a constant Ge content higher than the Ge content of first SiGe seed layer on the first SiGe seed layer; epitaxial growing a third SiGe layer with a constant Ge content lower than the Ge content of the second SiGe layer; and forming a cap layer on the third SiGe layer.