Multi-layer SiP with Through-Mold Vias for High-Density Integration
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Solution Overview
Problem
The challenge in packaging for mobile electronic devices is to achieve a high-density interconnect package with a small form factor, which requires integrating multiple components efficiently while minimizing package size and optimizing routing distances between components.
Innovation Solution
A highly integrated system in package (SiP) is fabricated by integrating two layers of functional components in molding compounds before and after the buildup, with solder joining or adhesive bonding of the molding layers, allowing for efficient integration of active and passive components of varying heights and enabling shorter routing distances through conductive layer application, via formation, and metallization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple components are integrated into a single package to reduce system size, then the package density increases, but the manufacturing complexity increases
Solution Approach 1:
The package is divided into multiple layers (first layer with first components, second layer with second components) that can be manufactured and prepared separately before being joined together. This segmentation allows each layer to be optimized independently while achieving high overall package density when assembled.
Solution Approach 2:
The patent transitions from planar component arrangement to three-dimensional multi-layer stacking, utilizing the vertical dimension to increase package density. Multiple components are arranged across different z-heights in separate layers, enabling higher integration without increasing the planar footprint.
2Volume of moving object
If components are arranged in a compact layout to minimize package size, then the form factor reduces, but the routing distance optimization becomes more difficult
Solution Approach 1:
By utilizing multiple layers stacked in the vertical dimension, the patent enables three-dimensional routing paths between components. This allows signal and power traces to travel through via holes connecting different layers, optimizing routing distances without increasing the planar package footprint.
Solution Approach 2:
Different layers are assigned specific functional roles (first layer with first components, second layer with second components) and local routing patterns are optimized for each layer's specific requirements. This localized optimization enables efficient routing within each layer while maintaining compact overall package dimensions.
3Reliability
If through-mold vias and through-silicon vias are used to connect layers, then the electrical connectivity is improved, but the manufacturing process complexity increases
Solution Approach 1:
Via holes are formed and conductive plugs are deposited in the mold compound layers before the semiconductor dies are mounted. This preliminary preparation of interconnect structures allows for more reliable electrical connections between layers, as the vias are established while the mold material is still in a suitable state for via formation.
Solution Approach 2:
The patent implements a nested structure where through-mold vias are formed within the mold compound layers, and through-silicon vias are formed within the semiconductor dies, with both types of vias working together to establish electrical connectivity across multiple layers. The vias are nested within the respective materials and connected through metallization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of multiple components with reduced package size, optimized routing, and efficient attachment of passive and active components, supporting fan-in and fan-out configurations and providing reliable connections without additional plating processes.
Implementation Method 1
a first semiconductor die and a first set of passive components are mounted on a first substrate and are at least partially surrounded by a first molding compound
Implementation Method 2
via holes formed through the first molding compound and the first substrate are plated with a conductive material and are filled with solder
Implementation Method 3
conductive layer application, via formation, and metallization
Data Source
AI summary
Embodiments herein relate to a system in package (SiP). The SiP may have a first layer of one or more first functional components with respective first active sides and first inactive sides opposite the first active sides. The SiP may further include a second layer of one or more second functional components with respective second active sides and second inactive sides opposite the second active sides. In embodiments, one or more of the first active sides are facing and electrically coupled with one or more of the second active sides through a through-mold via or a through-silicon via.