Multilayer SOI Structure With Segmented FD-SOI and RF-SOI Regions
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Solution Overview
Problem
Existing semiconductor-on-insulator structures, particularly double-BOX FD-SOI structures, are incompatible with both digital and radiofrequency applications due to electrical losses in the substrate and limited maximum power ratings, which hinder the development of high-quality PN junctions and radiofrequency components.
Innovation Solution
A semiconductor-on-insulator structure with a high-resistivity carrier substrate, multiple insulating layers, and a charge-trapping layer, combined with FD-SOI and RF-SOI regions, allowing for the integration of digital and radiofrequency components by optimizing the thickness and nature of the insulating layers and incorporating a charge-trapping layer to manage electrical charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-resistivity substrate is used to compensate for electrical losses in RF applications, then RF performance is improved, but the substrate becomes incompatible with transistors requiring back bias voltage control
Solution Approach 1:
The patent divides the semiconductor structure into distinct regions: an RF-SOI region with high-resistivity substrate for RF components, and an FD-SOI region with doped substrate for digital transistors requiring back bias control. This segmentation allows each region to be optimized for its specific function without compromise.
Solution Approach 2:
The patent applies different substrate properties to different locations: the first substrate region has high electrical resistivity for RF applications, while the second substrate region has doped regions for digital applications. This local differentiation resolves the contradiction by providing appropriate substrate characteristics where needed.
2Reliability
If a charge-trapping layer is added to improve RF performance, then electrical losses are compensated, but the layer hinders back biasing and accelerates dopant diffusion
Solution Approach 1:
The charge-trapping layer is selectively applied only in the RF-SOI region, not in the FD-SOI region. This segmentation allows the charge-trapping functionality to be implemented where needed for RF performance without interfering with digital transistor fabrication and back bias control.
Solution Approach 2:
The charge-trapping layer is positioned locally in the RF-SOI region to compensate for electrical losses, while its absence in the FD-SOI region preserves back bias control and prevents dopant diffusion issues. This local application resolves the contradiction between RF performance improvement and manufacturing quality.
3Reliability
If double-BOX structures are used for digital applications, then electrostatic characteristics are improved, but the structure becomes incompatible with radiofrequency applications due to limited power ratings
Solution Approach 1:
The patent creates separate FD-SOI and RF-SOI regions with different BOX layer configurations. The FD-SOI region uses double-BOX structure for improved electrostatic characteristics in digital applications, while the RF-SOI region uses a single BOX layer with high-resistivity substrate for high power ratings in RF applications.
Solution Approach 2:
Different BOX layer structures are applied to different regions: double-BOX in the FD-SOI region for digital devices needing electrostatic control, and single-BOX in the RF-SOI region for RF devices needing high power handling. This local differentiation resolves the power rating limitation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances both digital and radiofrequency performance by reducing electrical losses, enabling higher breakdown voltages and improved control of threshold voltage, thus supporting the fabrication of high-quality transistors and radiofrequency components.
Implementation Method 1
it is known to use a substrate, in particular, an SOI substrate, having a high electrical resistivity, this type of substrate commonly being referred to as an "HR substrate" for high-resistivity substrate. The latter is advantageously combined with a charge-trapping layer, i.e., a trap-rich layer.
Implementation Method 2
forming a weakened zone in the first donor substrate, so as to delineate an intermediate first semiconductor layer
Data Source
AI summary
The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.