Multilayer Solderable Layer for Power Semiconductor Chip Connections
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Solution Overview
Problem
Existing chip manufacturing processes for power semiconductor modules face challenges in achieving reliable soldered connections with high mechanical strength and electrical conductivity, particularly when subjected to repeated heating, which can lead to cavity formation due to solder penetration through metallic layers.
Innovation Solution
A soldering layer formed from Ni or Ni/V alloy with strategically introduced interfaces during the coating process prevents melt penetration, combined with a base layer of aluminum and intermediate layers like Ti or Cr to enhance adhesion and barrier properties, and a sputtering process with controlled interruptions to manage crystal growth and pore frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous coating process is used to produce the soldering layer, then the manufacturing process is simple and inexpensive, but the soldering layer lacks internal barriers that prevent melt penetration through the layer structure
Solution Approach 1:
The soldering layer is segmented into multiple sub-layers by interrupting the coating process, creating internal interfaces that act as barriers to melt penetration. This segmentation prevents the continuous formation of cavities while maintaining process simplicity
Solution Approach 2:
The coating process is deliberately interrupted during deposition to pre-form interfaces within the soldering layer before the actual soldering operation. This preliminary action creates barrier structures that prevent harmful melt penetration during subsequent heating
2Adaptability or versatility
If the soldering layer is heated to 200-250°C multiple times during manufacturing, then multiple soldering connections can be produced, but the soldering layer melts again and penetrates through other metal layers forming cavities
Solution Approach 1:
Interfaces are pre-formed within the soldering layer during coating to create barrier structures that cushion against and prevent harmful melt penetration during subsequent reheating operations. These interfaces act as stoppers that block the harmful effect of melt migration
Solution Approach 2:
The controlled interruption of the coating process creates interfaces that initially seem to add complexity, but these interfaces actually benefit the structure by preventing cavity formation. The interfaces convert the potential harm of melt penetration into a beneficial barrier effect
3Reliability
If interfaces are formed by interrupting the coating process during soldering layer production, then melt penetration is prevented and process reliability is improved, but the coating process becomes more complex
Solution Approach 1:
The coating process is segmented into multiple deposition stages with intentional interruptions, creating a multi-interface soldering layer structure. This segmentation approach improves reliability by forming barrier interfaces while maintaining relative process simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures robust mechanical strength and electrical conductivity of the soldered joint, preventing cavity formation and maintaining process reliability even at elevated temperatures, while maintaining a cost-effective and simple production method.
Implementation Method 1
a layer structure for producing a soldered connection is provided on a chip, which consists of several successive metal layers produced by means of a physical coating method such as sputtering
Implementation Method 2
a solder layer which at least partially melts together with the solder during the production of the soldered connection
Data Source
Figure 1~2
AI summary
The invention relates to a chip in which a layered structure (2) for producing a solder joint is provided on one side of a chip body (1) formed from a semiconducting material, wherein the layered structure (2) is formed from several successive metal layers (3, 4, 5, 6) produced by a physical coating process, and wherein a solderable solder layer (5) is provided between a noble metal layer (6) located on a surface of the layered structure (2) and the chip body (1). To prevent an undesired breakdown of a solder (7) through the layered structure (2), it is proposed according to the invention that the solder layer (5) has at least one interface (G1, G2) formed by an interruption of the coating process.