Multilayer Source/Drain Structure for Nanosheet Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a smaller area, including issues with trench formation, multilayer stack deposition, and the formation of nanostructure devices, which require precise etching and deposition processes to achieve efficient device performance.
Innovation Solution
A method involving the formation of a multilayer stack with alternating semiconductor materials, followed by trench formation and recess etching to create nanostructure devices, using techniques like epitaxial growth, chemical mechanical planarization, and reactive ion etching to achieve precise control over layer thickness and device structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and process control become more difficult
Solution Approach 1:
The source/drain region is segmented into multiple layers (first source/drain layer and second source/drain layer) with different materials and doping concentrations. This segmentation allows each layer to be optimized independently for specific functions, enabling precise control over carrier concentration and device performance even at reduced feature sizes.
Solution Approach 2:
Different regions of the source/drain structure are assigned different material compositions and doping concentrations. The first source/drain layer has a first doping concentration while the second source/drain layer has a second doping concentration, creating local quality variations that enable precise control of electrical characteristics in specific areas of the device.
2Reliability
If multilayer stack deposition is used to create nanostructure devices, then device performance can be improved, but process complexity increases
Solution Approach 1:
The first source/drain layer is formed and partially recessed before the second source/drain layer is deposited. This preliminary action creates a prepared substrate with specific geometric features and material properties that guide subsequent processing steps, enabling controlled formation of the multilayer structure with reduced process complexity.
Solution Approach 2:
The second source/drain layer is deposited over and integrates with the first source/drain layer, creating a nested multilayer structure. The layers are positioned and dimensioned such that the second layer encompasses portions of the first layer, forming a compact integrated structure that achieves complex functionality through nested arrangement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-density semiconductor devices with improved integration density and performance by allowing for the formation of nanostructure devices with precise control over channel profiles and source/drain regions, enhancing device efficiency and reducing leakage current.
Implementation Method 1
a multilayer stack with alternating semiconductor materials, followed by trench formation and recess etching to create nanostructure devices, using techniques like epitaxial growth
Implementation Method 2
using techniques like epitaxial growth, chemical mechanical planarization, and reactive ion etching to achieve precise control over layer thickness and device structure
Implementation Method 3
using techniques like epitaxial growth, chemical mechanical planarization, and reactive ion etching to achieve precise control over layer thickness and device structure
Data Source
AI summary
Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.