Multilayer Source/Drain Regions for Scaled Nanosheet FETs

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining performance and reliability, particularly in forming high-density multilayer structures and patterning features.

Innovation Solution

A multilayer structure is formed using alternating layers of semiconductor materials with controlled deposition and etching processes, followed by the creation of patterned multilayer stacks and parasitic channels, which are then processed to form nanostructures with precise recess profiles and spacers, enabling the formation of advanced transistor architectures like gate-all-around MOSFETs and nanosheet FETs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but additional manufacturing challenges and reliability issues arise

Engineering Contradiction:

Improveintegration densityVSAvoidfeature size control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The source/drain region is divided into multiple layers (first source/drain layer and second source/drain layer) with different materials and doping types. This segmentation allows each layer to be optimized independently for specific functions, enabling better control at reduced feature sizes while maintaining manufacturing feasibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the source/drain structure are assigned different materials and doping characteristics. The first source/drain layer uses a first semiconductor material with first doping type, while the second source/drain layer uses a second semiconductor material with second doping type. This local differentiation optimizes performance for specific device regions while managing manufacturing complexity.

Inventive Principle:

Principle #3Local quality

2Productivity

If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but reliability issues arise

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The source/drain region employs a composite structure with two different semiconductor materials (first semiconductor material and second semiconductor material) having different doping types. This composite approach allows optimization of electrical properties, stress management, and carrier mobility, thereby maintaining device reliability at reduced feature sizes.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

Instead of using a single uniformly doped source/drain layer, the patent inverts the conventional approach by implementing a dual-layer structure with opposite doping types. This inversion enables better control of electric fields and carrier transport, improving device performance and reliability at scaled dimensions.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances integration density and performance of semiconductor devices by allowing for more efficient formation of multi-channel devices, improving the integration of active components and reducing feature size limitations.

Implementation Method 1

A multilayer structure is formed using alternating layers of semiconductor materials with controlled deposition and etching processes

Methodology Applied

Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

A multilayer structure is formed using alternating layers of semiconductor materials with controlled deposition and etching processes

Methodology Applied

Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

followed by the creation of patterned multilayer stacks and parasitic channels, which are then processed to form nanostructures with precise recess profiles

Methodology Applied

Scientific EffectPlasma etching: Plasma

Data Source

PatentUS20250338566A1Semiconductor devices having a multilayer source/drain region and methods of manufacture

Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.