Multilayer Source/Drain Stressor Epitaxy for Carrier Mobility
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Solution Overview
Problem
The reduction in transistor size and increased integration in semiconductor devices leads to reduced turn-on current and deteriorated performance, affecting the reliability and operating speed of semiconductor devices, necessitating improvements in carrier mobility within the channel region.
Innovation Solution
The semiconductor device incorporates a substrate with a gate pattern, a base epitaxial pattern, and a bulk epitaxial pattern on the substrate's recess region, where the base epitaxial pattern has varying thicknesses on different crystal planes and a lower dopant concentration, formed through selective epitaxial growth processes to apply specific stresses and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor size is reduced for high integration, then device density increases, but turn-on current decreases and performance deteriorates
Solution Approach 1:
The patent applies different stress conditions to different regions of the transistor channel. Specifically, it creates a stressor structure with varying thickness: a first thickness in the first region and a second thickness greater than the first thickness in the second region. This local variation in stressor thickness provides enhanced stress effect in the second region while maintaining overall device integration, thereby improving carrier mobility and turn-on current without sacrificing integration density.
2Quantity of substance
If transistor size is reduced for high integration, then device density increases, but operating speed decreases
Solution Approach 1:
The patent implements a locally optimized stressor structure where the second region has a greater stressor thickness compared to the first region. This localized enhancement of stress in the second region improves carrier mobility specifically where needed, thereby increasing operating speed while maintaining the reduced overall transistor size required for high integration density.
3Ease of manufacture
If uniform stressor thickness is used, then manufacturing is simpler, but carrier mobility enhancement is insufficient
Solution Approach 1:
The patent employs a stressor structure with non-uniform thickness, having a first thickness in the first region and a second thickness in the second region, where the second thickness is greater than the first thickness. This local quality variation optimizes carrier mobility enhancement in the second region without significantly complicating the manufacturing process, as the stressor can still be formed using standard epitaxial growth techniques with controlled doping profiles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases carrier mobility and reduces leakage current, thereby enhancing the performance and reliability of semiconductor devices by applying compressive or tensile forces to the channel region, improving the turn-on current and operating speed.
Implementation Method 1
a base epitaxial pattern on an inner surface of a recess region in the substrate at a side of the gate pattern. The inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes.
Implementation Method 2
This configuration increases carrier mobility and reduces leakage current, thereby enhancing the performance and reliability of semiconductor devices by applying compressive or tensile forces to the channel region
Data Source
AI summary
A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.