Multilayer Spacer Decoupling for Memory Device Silicide Masks
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Solution Overview
Problem
The formation of dielectric spacers and silicide protection masks in memory devices is challenging due to conflicting requirements for thickness, leading to suboptimal geometrical characteristics in both circuitry and array areas.
Innovation Solution
A process involving the formation of multilayer spacers using a combination of oxide and nitride layers, allowing independent selection of spacer length and silicide protection mask thickness, decoupling these parameters for optimal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the thickness of the dielectric layer is increased to obtain the desired length of dielectric spacers, then the spacer length is improved, but the silicide protection mask becomes excessively thick and cannot be defined without damaging existing structures in the circuitry area
Solution Approach 1:
The dielectric layer is segmented into two separate layers: a first dielectric layer (oxide) and a second dielectric layer (nitride). The first layer forms the spacers in the circuitry area with controlled thickness, while the second layer forms the silicide protection mask in the array area. This segmentation allows independent thickness optimization of each layer for its specific function, resolving the contradiction between spacer length and mask definability.
Solution Approach 2:
Different dielectric materials are used in different areas: oxide is used where spacers are needed (circuitry area) and nitride is used where protection masks are needed (array area). Each material is selected for its specific properties - oxide provides the desired spacer characteristics while nitride provides the required mask characteristics. This local differentiation allows each region to have optimal properties for its specific function.
2Ease of manufacture
If the thickness of the dielectric layer is decreased to enable proper silicide protection mask definition, then the mask definition is improved, but the dielectric spacers become too narrow and fail to ensure correct geometrical characteristics for circuitry MOS transistors
Solution Approach 1:
The dielectric system is divided into two independent layers with independent thickness control. The first dielectric layer thickness is optimized for spacer formation (sufficiently thick to ensure correct geometrical characteristics), while the second dielectric layer thickness is optimized for mask definition (thin enough to be properly defined). This segmentation eliminates the trade-off present in single-layer designs.
Solution Approach 2:
The solution uses a composite dielectric structure combining two different materials (oxide and nitride) with different physical and chemical properties. This composite approach allows the structure to simultaneously exhibit the properties needed for both spacer formation and mask definition, as each material can be independently optimized for its specific role.
3Device complexity
If a single dielectric layer is used for both spacers and silicide protection mask, then the process is simplified, but the lateral width of spacers and mask thickness become dependent on each other, preventing independent optimization
Solution Approach 1:
The single dielectric layer is segmented into two separate layers, each with independent thickness control. This allows the lateral width of spacers (determined by the first layer thickness) and the mask thickness (determined by the second layer thickness) to be independently optimized without affecting each other, while still maintaining a relatively simple two-step deposition process.
Solution Approach 2:
The solution moves from a single-dimensional parameter control (one dielectric layer thickness controlling both spacer width and mask thickness) to a two-dimensional parameter space (two independent layer thicknesses). This dimensional expansion allows independent optimization of both critical dimensions without increasing process complexity significantly.
Data Source
AI summary
A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask.