Multilayer Spacer Matrix for Dense TFT Arrays With Lower Capacitive Coupling
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Solution Overview
Problem
Current transistor structures face challenges in achieving high-density integration without damaging existing devices and in reducing capacitive coupling between neighboring transistors, particularly in back-end-of-line (BEOL) integration.
Innovation Solution
The development of a self-aligned multilayer spacer matrix using thin film transistors with a semiconducting metal oxide active layer, which includes a first dielectric spacer matrix layer and a second dielectric spacer matrix layer that functions as an etch mask, allowing for the formation of source and drain cavities while minimizing electrical connections between access transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-density transistor integration is implemented, then device density and integration efficiency are improved, but capacitive coupling between neighboring transistors increases
Solution Approach 1:
The patent divides the dielectric structure into multiple layers: a first dielectric layer, a second dielectric layer with different material properties, and a third dielectric layer. This segmentation allows each layer to serve specific functions in reducing capacitive coupling while maintaining high device density. The second dielectric layer with lower dielectric constant is strategically positioned to minimize coupling between adjacent transistors.
Solution Approach 2:
The patent applies different dielectric materials with different properties to different regions and layers of the transistor structure. The second dielectric layer uses a material with lower dielectric constant specifically in regions where capacitive coupling needs to be reduced, while other layers maintain higher dielectric constants for electrical isolation and stability. This local optimization reduces harmful capacitive coupling without compromising overall device performance.
2Reliability
If fabrication processes are performed at high temperatures, then transistor performance is improved, but previously fabricated devices are damaged
Solution Approach 1:
The patent changes the temperature parameter of the fabrication process by using low-temperature processing techniques. The dielectric layers are deposited and processed at temperatures that are sufficient to achieve proper material formation and electrical characteristics but low enough to prevent damage to previously fabricated FEOL and MEOL devices. This parameter optimization allows transistor fabrication without compromising existing structures.
3Manufacturing precision
If spacer matrix layers are used for self-alignment, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements self-alignment by forming spacer matrix layers beforehand that define the precise locations of source and drain regions. The second dielectric layer is deposited conformally over the patterned first dielectric layer, creating spacers that automatically position subsequent structures with high precision. This preliminary formation of alignment structures eliminates the need for additional alignment steps and reduces manufacturing complexity despite the multi-layer dielectric structure.
Data Source
AI summary
A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.