Multi-Layer Spacer Structure for Low-Capacitance Conductive Lines
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Solution Overview
Problem
As semiconductor devices become highly integrated, the reduced spacing between wirings leads to increased parasitic capacitance, necessitating an improved wiring structure and fabrication method to reduce this capacitance.
Innovation Solution
A semiconductor device with a multi-layered spacer structure comprising a diffusion barrier material, a boron nitride layer, and an antioxidant material is used to cover conductive lines, specifically stacked in the order of a first boron-free nitride layer, a boron nitride layer, and a second boron-free nitride layer, which reduces parasitic capacitance by applying a low dielectric constant material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between wirings is reduced to achieve high integration, then device integration density is improved, but parasitic capacitance between wirings increases
Solution Approach 1:
The patent applies different materials with different dielectric constants to different regions of the spacer structure. The first spacer layer uses a material with dielectric constant 3.9-4.3, while the second spacer layer uses a material with dielectric constant 2.0-3.0, creating local quality variation that reduces parasitic capacitance in the critical region between adjacent bit lines while maintaining overall structural integrity
Solution Approach 2:
The patent employs a composite multi-layer spacer structure combining materials with different dielectric properties. This composite structure allows the device to achieve both high integration density and reduced parasitic capacitance by strategically placing low-k material layers where capacitance reduction is most critical
2Ease of manufacture
If a simple single-layer spacer structure is used to reduce manufacturing complexity, then ease of manufacture is improved, but ability to control parasitic capacitance and prevent material diffusion is reduced
Solution Approach 1:
The spacer structure is segmented into multiple functional layers: a first spacer layer for initial coverage, a boron nitride layer for diffusion barrier functionality, and a second spacer layer for additional capacitance reduction. This segmentation allows each layer to perform its specific function optimally while maintaining overall manufacturing feasibility
Solution Approach 2:
The multi-layer spacer structure serves multiple functions simultaneously: it reduces parasitic capacitance through low-k materials, prevents boron diffusion through the boron nitride barrier layer, and provides structural support. This multi-functionality achieves reliability enhancement without proportionally increasing manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-layered spacer structure effectively reduces parasitic capacitance and improves the reliability of semiconductor devices by utilizing a low dielectric constant material similar to air gaps, simplifying the semiconductor process and preventing boron diffusion and oxidation.
Implementation Method 1
a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer
Implementation Method 2
a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material
Implementation Method 3
reduces parasitic capacitance by applying a low dielectric constant material
Data Source
AI summary
Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.