Multi-Layer SRAM Device Structure With Hierarchical Control
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Solution Overview
Problem
Existing SRAM devices face challenges in optimizing speed and power consumption due to the trade-off between shortened local bit lines and prolonged global bit lines and word-line-decoder lines when dividing the SRAM array into multiple sub-arrays, which affects overall device performance.
Innovation Solution
A multi-layer semiconductor device structure is implemented, featuring device layers with SRAM arrays, word-line drivers, layer decoders, local input/output circuits, and global control/input/output circuits, where the global control circuit decodes input signals to activate the appropriate layer decoder and bit lines, and global input/output circuits transmit data across layers, optimizing access to target SRAM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If global control circuits are used to activate layer decoders across multiple device layers, then access to target SRAM cells is optimized, but device complexity increases
Solution Approach 1:
The patent divides the control circuitry into hierarchical levels: global control circuits that manage inter-layer coordination and layer decoders that handle local word-line activation. This segmentation allows each control component to have a focused, simplified function while the hierarchical structure achieves complex cross-layer access optimization.
Solution Approach 2:
The global control circuits are designed to universally manage access to target SRAM cells across multiple device layers using a standardized control mechanism. This multi-functional approach allows the same global control structure to handle access to any layer, reducing overall system complexity compared to having dedicated control circuits for each layer.
Data Source
AI summary
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.