Multi-Layer SRAM Transistor Layout for Smaller Memory Cells
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Solution Overview
Problem
Memory devices, such as SRAM cells, consume a large area due to all transistors being formed on a single layer, which increases fabrication costs and may hinder performance improvements.
Innovation Solution
Transistors in memory cells are formed on both upper and lower layers, with some transistors fabricated using back-end-of-line (BEOL) processes, reducing the overall area requirement and fabrication costs while maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all transistors are formed on a single layer, then fabrication process is simpler, but area consumption increases
Solution Approach 1:
The patent transitions from a planar single-layer transistor arrangement to a three-dimensional multi-layer structure. Specifically, it forms a first transistor in a first layer and a second transistor in a second layer vertically above the first layer, thereby utilizing the vertical dimension to reduce the horizontal area footprint of the memory cell while maintaining functional integrity
2Device complexity
If all transistors are formed on a single layer, then device structure is simpler, but area consumption increases
Solution Approach 1:
The invention introduces vertical stacking of transistors across multiple layers, transforming the device architecture from two-dimensional planar layout to three-dimensional stacked configuration. This dimensional transition reduces the lateral area requirement by exploiting the vertical space, accepting increased structural complexity as a necessary trade-off for area reduction
3Area of moving object
If transistors are formed on multiple layers, then area consumption is reduced, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the first transistor in the first layer, then forming the second transistor in the second layer above it. This segmentation allows each layer to be processed and optimized independently, managing the overall fabrication complexity by breaking down the multi-layer construction into manageable sequential steps
4Area of moving object
If transistors are formed on multiple layers, then area consumption is reduced, but device structure complexity increases
Solution Approach 1:
The patent deliberately introduces vertical stacking of transistors across multiple layers, transforming the device architecture from two-dimensional planar layout to three-dimensional stacked configuration. This dimensional transition reduces the lateral area requirement by exploiting the vertical space, accepting increased structural complexity as a necessary trade-off for area reduction
Data Source
AI summary
A semiconductor device including a substrate, a first layer over the substrate, and a second layer over the first layer. The first layer including a first fin structure, a first gate structure that overlaps the first fin structure to form a first pass-gate transistor, and a second gate structure that is separate from the first gate structure and that overlaps the first fin structure to form a first pull-down transistor. The second layer including a third gate structure disposed over the second gate structure and connected to the second gate structure, a first semiconductor oxide structure disposed on the third gate structure, and a first drain/source region and a second drain/source region disposed on the first semiconductor oxide structure, wherein the third gate structure, the first semiconductor oxide structure, the first drain/source region, and the second drain/source region constitute a first pull-up transistor.