Multilayer Package Substrate With Lead Pad Crack Stop Structure
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Solution Overview
Problem
Delamination and crack propagation between leads and mold compound in microelectronic device packages lead to mechanical stress and failure during assembly and use, particularly in SOIC packages, causing scrapped devices.
Innovation Solution
A multilayer package substrate with trace and connection conductor layers is used, coupled by dielectric material, and leadframes with partially etched lead pads to form a crack stop feature, preventing crack propagation to solder joints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If leads are extended through mold compound to form exterior terminals, then device functionality is improved, but delamination and crack propagation occur between leads and mold compound
Solution Approach 1:
The lead structure is segmented into three distinct portions: an exterior portion extending through the mold compound, an interior portion within the mold compound, and a lead pad at the interface. This segmentation allows each portion to be optimized independently - the lead pad provides a stable bonding interface while the interior and exterior portions maintain electrical connectivity and terminal functionality.
Solution Approach 2:
Different portions of the lead have different thicknesses to serve different functions. The lead pad has a first thickness optimized for bonding to the package substrate, while the interior and exterior portions have a second thickness (greater than the first) optimized for mechanical strength and electrical conductivity. This local variation in quality prevents crack propagation while maintaining device functionality.
2Adaptability or versatility
If leads move during assembly processes, then flexibility is improved, but cracking and delamination occur at mold compound interface
Solution Approach 1:
The thicker interior portion of the lead acts as a cushioning element that absorbs and distributes mechanical stresses during assembly processes. This pre-engineered stress distribution prevents cracks from forming at the vulnerable mold compound interface, allowing the leads to move flexibly without compromising interface integrity.
3Reliability
If crack propagation occurs from exterior boundary, then device functionality is compromised, but crack stop feature prevents this
Solution Approach 1:
The lead structure is segmented into distinct portions with different thicknesses, creating a stepped configuration that acts as a crack stop feature. This segmentation provides crack propagation resistance while maintaining relatively simple manufacturing processes and device functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The crack stop feature increases the reliability of microelectronic device packages by preventing crack propagation to solder joints, reducing failures and device scrapping.
Implementation Method 1
mounting the package substrate to inner portions of the leads of the leadframe by solder joints
Data Source
AI summary
An example microelectronic device package includes: a leadframe having leads extending from an exterior portion to an interior portion and having lead pads at an end of the interior portion, the lead pads having a first thickness that is less than the a second thickness of the leads; a multilayer package substrate including conductors spaced from one another by dielectric material, a board side surface of the multilayer package substrate mounted to the leadframe by solder joints on the lead pads; at least two semiconductor dies mounted to a device side surface of the multilayer package substrate opposite the board side surface; mold compound covering the multilayer package substrate, the at least two semiconductor dies, the lead pads, and the interior portions of the leads, the exterior portions of the leads free from the mold compound; and the exterior portions of the leads forming terminals for the microelectronic device package.