Multilayer Substrate Lead Wiring Layout for Burr-Free Cutlines
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Solution Overview
Problem
The challenge is to enhance circuit density and electrical characteristics while minimizing the formation of lead wiring in cutline areas, which can lead to burrs, metallic foreign matter, and noise in circuit boards, and reduce productivity due to additional processing requirements for removing lead wiring.
Innovation Solution
A multilayer substrate design featuring insulating layers with defined cutline areas, circuits with or without plating layers, vias for connectivity, and lead wiring extending to the cutline area, allowing for efficient formation of a plating layer on selected layers without forming lead wiring in each layer, thereby reducing thickness and exposure of metal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lead wiring is formed in the cutline area of each layer to increase circuit density, then circuit density is improved, but the thickness of target patterns increases leading to burrs and metallic foreign matter
Solution Approach 1:
The patent extracts lead wiring from the cutline area by positioning it in the non-cutline area, eliminating the source of burrs and metallic foreign matter while maintaining circuit density through alternative lead wiring configurations
2Quantity of substance
If lead wiring is formed in the cutline area of each layer, then circuit density is improved, but wiring is excessively exposed on the sides causing noise
Solution Approach 1:
The patent removes lead wiring from the cutline area where it would be excessively exposed, thereby eliminating the source of electromagnetic noise while maintaining circuit functionality through repositioned lead wiring in non-cutline areas
3Manufacturing precision
If lead wiring is removed before forming upper layer circuitry, then burrs and metallic foreign matter are reduced, but additional masking processes are required decreasing productivity
Solution Approach 1:
The patent performs preliminary positioning of lead wiring in non-cutline areas during the circuit board formation process, preventing the need for subsequent removal operations and masking processes, thereby maintaining cutting quality while preserving productivity
4Quantity of substance
If patterns are overlapped to increase thickness for high circuit density, then circuit density is improved, but lead wiring thickness in cutline area increases leading to burrs
Solution Approach 1:
The patent extracts lead wiring from the cutline area entirely, allowing patterns to be overlapped for high circuit density without the compounding effect of lead wiring thickness that would otherwise create burrs during cutting
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of burrs and noise, maintains product quality, and enhances circuit density and electrical characteristics by allowing for efficient lead wiring design and high-density circuit implementation.
Implementation Method 1
circuits with or without plating layers
Data Source
AI summary
Provided are: a multilayer substrate in which a single portion of leading wiring can be used to increase circuit density and enhance electrical characteristics; a method for manufacturing same; and an electronic device including the multilayer substrate. The multilayer substrate comprises: a plurality of insulating layers each having a defined cut line region; circuits which are formed on the respective insulating layers and including wiring and a plating layer or only wiring; a via formed in at least one insulating layer among the plurality of insulating layers; and leading wiring which is formed on one insulating layer among the plurality of insulating layers and connects the cut line region and the wiring, wherein the plating layers are formed on the surface of the wiring by using an electrical signal supplied to the leading wiring.