Multilayer Substrate Routing for Fanout Wafer-Level Packaging
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Solution Overview
Problem
Current fanout routing technology for wafer-level BGA packages is capital-intensive and constrained by capacity, making it difficult to keep up with the increasing demand for smaller, higher-pin-count packages while maintaining profit margins.
Innovation Solution
The method involves forming integrated circuit packages with substrates encapsulated in a mold compound, eliminating the need for expensive fanout routing equipment by using existing substrate manufacturing infrastructure and leveraging multilayer substrates instead of redistribution layers, allowing for efficient and cost-effective production of small-sized packages with high pin counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fanout routing technology is used for wafer-level BGA packages, then routing capability is improved, but capital investment and manufacturing cost increase significantly
Solution Approach 1:
Instead of extending routing outward from the die (fanout), the patent inverts the approach by bringing routing inward through substrate layers beneath the die. This substrate routing approach eliminates the need for expensive fanout routing equipment while achieving the same routing capability through multilayer substrate construction.
Solution Approach 2:
The patent introduces multilayer substrates as an intermediary between the die and the external connections. These substrates provide the routing functionality that would otherwise require fanout routing equipment, enabling cost-effective manufacturing while maintaining routing versatility through multiple substrate layers.
2Adaptability or versatility
If fanout routing technology is used, then routing flexibility is improved, but manufacturing capacity is constrained
Solution Approach 1:
The patent segments the routing function across multiple substrate layers rather than requiring a single complex fanout routing step. This segmentation allows different routing layers to be manufactured using standard substrate processes, increasing manufacturing capacity while maintaining routing flexibility through the stacked substrate architecture.
Solution Approach 2:
The patent moves routing from the horizontal plane (fanout on die surface) to the vertical dimension (through multilayer substrates stacked beneath the die). This dimensional transition enables routing flexibility through layer stacking while accommodating high-volume manufacturing using established substrate fabrication capabilities.
3Productivity
If wafer-level packaging is increased to meet demand, then output volume is improved, but cost competitiveness decreases due to heavy capital investment
Solution Approach 1:
The patent makes standard substrate manufacturing equipment perform the routing function that would otherwise require specialized fanout routing equipment. By using multilayer substrates with embedded routing, existing substrate fabrication tools can produce wafer-level packages at high volume without the need for expensive dedicated fanout routing capital equipment, maintaining cost competitiveness while scaling output.
Data Source
AI summary
Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.