Multilayer TFT Aperture Ratio via Vertical Stacking
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Solution Overview
Problem
Conventional thin film transistor (TFT) manufacturing techniques for active matrix displays face challenges in achieving high aperture ratios due to limitations in printing resolution and conductivity of metallic interconnect lines, particularly when using flexible substrates and solution-based print processes, which result in low capacitance and insufficient device performance.
Innovation Solution
A multilayer electronic structure with a thin film transistor and capacitor, featuring at least four conducting layers separated by three dielectric layers, where the gate electrode is in a separate conducting layer from the capacitor, allowing for increased alignment tolerance and enhanced capacitance without compromising the aperture ratio, suitable for solution deposition techniques like direct write printing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional printing processes are used to fabricate metallic interconnect lines, then manufacturing cost is reduced and flexibility is enabled, but linewidth control deteriorates and conductivity decreases
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D multi-layer stacking, where interconnect lines are distributed across multiple vertical layers. This dimensional change allows each layer to use relaxed printing techniques while achieving fine effective linewidth through precise layer registration, resolving the contradiction between low-cost printing and linewidth control.
Solution Approach 2:
The patent segments the interconnect structure into multiple conducting layers separated by dielectric layers. Each layer can be independently fabricated using printing processes with relaxed precision requirements, while the cumulative effect of multiple segments achieves the equivalent of a single fine-pitch interconnect, resolving the linewidth control issue.
2Reliability
If thick and wide interconnect lines are used to compensate for low conductivity, then adequate conductance is achieved, but aperture ratio deteriorates
Solution Approach 1:
The patent moves interconnect lines from the 2D plane to the 3D vertical dimension by stacking multiple conducting layers. This allows the use of wider individual lines (better for conductivity) while maintaining high aperture ratio because the lines are distributed vertically rather than competing for horizontal space in a single layer.
Solution Approach 2:
The patent segments the conductive path into multiple parallel layers, where each layer contributes to the overall conductance. This segmentation allows each individual interconnect line to be optimized for conductivity with adequate width, while the multi-layer architecture prevents any single layer from dominating the aperture ratio.
3Device complexity
If gate electrode and capacitor are in the same conducting layer, then device complexity is reduced, but alignment precision deteriorates and capacitance is limited
Solution Approach 1:
The patent separates the gate electrode and capacitor into different vertical layers (gate in one conducting layer, capacitor in another). This vertical separation in the third dimension provides inherent alignment tolerance, as the larger vertical spacing is less sensitive to lateral registration errors than in-plane alignment, resolving the contradiction between simplicity and alignment precision.
4Manufacturing precision
If high-resolution photolithography is used to achieve fine linewidths, then manufacturing precision is improved, but manufacturing cost increases and flexibility is lost
Solution Approach 1:
The patent uses multi-layer stacking to achieve fine effective linewidth without requiring high-resolution in-plane patterning. Each layer can be printed with relaxed precision, and the vertical stacking provides the necessary precision through layer registration, eliminating the need for expensive high-resolution photolithography equipment and processes.
Data Source
AI summary
A multiple layer pixel architecture for an active matrix display is provided having a common bus line on a metal level separate from that on which the gate electrodes of the thin-film transistors (TFTs) are formed. A multilayer electronic structure includes a TFT for driving a pixel of an active matrix optoelectronic device and a capacitor for storing charge to maintain an electrical state of said active matrix pixel, wherein the structure includes a substrate bearing at least four conducting layers separated by at least three dielectric layers, first and second ones of said conducting layers defining drain/source electrodes and a gate electrode of said transistor respectively, and third and fourth ones of said conducting layers defining respective first and second plates of said capacitor, wherein said capacitor and said transistor are laterally positioned such that they overlap in a vertical direction.