Multilayer TFT Semiconductor Regions for Precise Contact Etching
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Solution Overview
Problem
As integrated circuits scale downward in size, challenges arise with forming backend structures due to process variations leading to inconsistent transistor performance and low yield, particularly in forming contact recesses in thin film transistor structures, which affect device performance and reliability.
Innovation Solution
The implementation of multilayer and concentration gradient semiconductor regions in thin film transistor structures, allowing for controlled etch rates and improved contact resistance, thermal stability, and consistent drive current through compositionally different layers and material gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-layer semiconductor region is used, then the structure is simple and manufacturing is easier, but etch rate control is imprecise leading to high contact resistance
Solution Approach 1:
The semiconductor region is divided into multiple layers with different compositions (e.g., InGaZnO4, InGaO3, InGaO4) or doping concentrations. Each layer has distinct etch rates, allowing precise control of contact etching depth and improving contact resistance without requiring complex external control mechanisms.
Solution Approach 2:
Different layers within the semiconductor region are assigned different material compositions or doping concentrations to create local variations in etch rate. This allows the etching process to naturally stop at desired depths by exploiting the inherent differences in etch selectivity between layers, achieving precise manufacturing control.
2Reliability
If contact etching is performed without precise control, then the process is simpler and faster, but device performance becomes inconsistent
Solution Approach 1:
The semiconductor region is pre-structured with multiple layers of different compositions or doping concentrations before the contact etching process. This preliminary structuring ensures that the subsequent etching process automatically achieves consistent results across different devices, improving reliability without requiring complex real-time control during manufacturing.
Solution Approach 2:
The material composition or doping concentration parameters are varied across different layers of the semiconductor region. These parameter changes create distinct etch rate characteristics in each layer, enabling consistent etching depth control and improving device performance consistency across production batches.
3Reliability
If higher doping concentration is used in semiconductor region, then contact resistance decreases, but carrier mobility may be reduced due to impurity scattering
Solution Approach 1:
The semiconductor region is segmented into multiple layers with different doping concentrations. The lower layer can have higher doping to reduce contact resistance, while upper layers have lower doping to maintain high carrier mobility, thus resolving the trade-off between contact resistance and carrier mobility through spatial segmentation.
Solution Approach 2:
Different regions of the semiconductor structure are assigned different doping concentrations tailored to their specific functional requirements. Contact regions receive higher doping for low resistance, while channel regions maintain lower doping for high mobility, achieving optimal performance in each location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by reducing process variations, improving etch precision, and increasing thermal stability, leading to more reliable and consistent device operation.
Implementation Method 1
The different layers (or concentration gradient(s) within a given layer, as the case may be) allow for different etch rates through each layer to controllably form contact recesses
Implementation Method 2
a given layer may include a concentration gradient of one or more materials or dopants through a thickness of the given layer
Data Source
AI summary
Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.