Multi-layer Thyristor RAM with Silicon-Germanium Bases
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Solution Overview
Problem
Conventional DRAM technologies face challenges in scaling down memory cell area while maintaining capacitance and reducing transistor leakage, with alternative thyristor-based designs struggling with data retention and process control, especially in small geometry cells.
Innovation Solution
A multi-layer random access memory array is developed with thyristor memory cells stacked vertically, connected by vertical electrical connections, and using select transistors and assist gates to enable random access, along with a manufacturing process involving confined epitaxial lateral overgrowth of crystalline silicon and silicon-germanium base regions to improve switching characteristics and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional DRAM cell structures are used to increase bit density, then cell area is reduced, but capacitance value deteriorates and transistor leakage increases
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangements to a 3D vertical stacked architecture. Multiple memory layers are stacked vertically with through-silicon vias (TSVs) connecting corresponding cells across layers, enabling increased bit density without further reducing the footprint of individual cells. This dimensional change allows maintaining adequate capacitance and leakage characteristics while achieving higher storage capacity.
2Adaptability or versatility
If thyristor-based memory cells are used to overcome scaling challenges, then alternative cell designs are achieved, but data retention deteriorates in small geometry cells
Solution Approach 1:
The thyristor structure is segmented into multiple discrete layers (first through fourth semiconductor layers forming p-n-p-n regions) stacked vertically. This segmentation allows each layer to be independently optimized for specific functions while maintaining overall data retention characteristics. The vertical separation of charge storage regions from access regions enables better control of retention properties in scaled geometries.
Solution Approach 2:
Different regions of the thyristor structure are assigned different doping concentrations and material compositions optimized for their specific functions. The base regions have specific doping levels for charge storage, while the emitter and collector regions have different compositions for efficient carrier injection and collection. This local optimization maintains data retention in small geometry cells.
3Ease of manufacture
If epitaxial or CVD semiconductor layers are added at backend of CMOS process, then thyristor cells are formed, but device performance and yield deteriorate
Solution Approach 1:
The thyristor structure is formed using epitaxial growth as a preliminary step before the main CMOS fabrication process. The semiconductor layers are grown with predetermined doping profiles and compositions, establishing the p-n-p-n structure in advance. This preliminary formation allows subsequent CMOS processing to proceed without additional high-temperature steps that would degrade existing devices, thereby maintaining performance and yield.
4Reliability
If pnpn devices are operated in breakdown regime for data writing, then data storage is achieved, but power consumption and process control challenges increase
Solution Approach 1:
The operating parameters of the pnpn device are changed from breakdown regime to forward active regime. Data is written by switching the thyristor between on and off states using controlled forward bias conditions rather than relying on reverse breakdown. This parameter change reduces power consumption during write operations and simplifies process control while maintaining data storage capability through the bistable nature of the forward-active pnpn structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution increases bit density per unit area, reduces patterning costs, and enhances data retention and switching speed while minimizing power consumption and minority carrier effects, addressing the limitations of conventional DRAM technologies.
Implementation Method 1
a manufacturing process involving confined epitaxial lateral overgrowth of crystalline silicon and silicon-germanium base regions
Data Source
AI summary
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.