Multi-Layer Transistor Layout for Low Parasitic Capacitance
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Solution Overview
Problem
High frequency MOSFETs face challenges in achieving high transconductance, cut-off frequency, and low noise due to high gate resistance and parasitic capacitance, which are exacerbated by the need to balance low current density and electro-migration design rules in high frequency analog circuits.
Innovation Solution
The design incorporates comb-shaped drain and source electrodes with varying levels of interleaving across multiple layers, optimized to reduce parasitic capacitance and maintain low current density, including reduced interleaving and shorter fingers further from the gate electrode, and a double-sided comb-shaped gate electrode to minimize resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If comb-shaped drain and source electrodes with interleaved fingers are used to reduce gate resistance, then high frequency performance is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies multi-layer electrode structure where drain and source electrodes are distributed across different metal layers (M1, M2, M3) instead of being planar. This vertical dimensionality reduces the overlapping area between opposing drain-source finger pairs, thereby reducing parasitic capacitance while maintaining the low gate resistance benefit of comb-shaped interleaved fingers in each layer
Solution Approach 2:
The comb-shaped electrodes are segmented into multiple fingers across multiple layers. Each layer contains interleaved drain and source fingers that connect to different contact regions. This segmentation allows current to be distributed through multiple parallel paths, reducing gate resistance while the spatial separation across layers reduces parasitic capacitance
2Speed
If finger length is increased to reduce gate resistance, then high frequency characteristics are improved, but electro-migration design rules are violated due to high current density
Solution Approach 1:
The patent distributes the electrode structure across multiple vertical layers (M1, M2, M3) instead of using a single planar layer. This vertical distribution increases the total cross-sectional area available for current flow, thereby reducing current density and preventing electro-migration while maintaining sufficiently long horizontal finger lengths for low gate resistance
Solution Approach 2:
Multiple metal layers are merged to form a composite electrode structure where drain and source connections are established through multiple parallel conductive paths across different layers. This merging provides redundant current paths that reduce current density in any single finger while maintaining the overall low resistance required for high frequency operation
Data Source
AI summary
An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.