Multi-Layer Trench Capacitor Layout for Small-Pitch Chips
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Solution Overview
Problem
As integrated chip technology advances, reducing the pitch of integrated chips leads to a reduction in the area available for trenches and trench capacitors, resulting in decreased capacitance without increasing the pitch.
Innovation Solution
Incorporating a plurality of parallelly coupled capacitors within a single trench, where each capacitor consists of multiple electrodes and insulative layers, coupled in parallel by contacts on either side of the trench, effectively increasing the capacitance without expanding the chip's pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of integrated chips is reduced, then the integration density is improved, but the area available for trenches and trench capacitors is reduced, resulting in decreased capacitance
Solution Approach 1:
The patent divides a single trench capacitor into multiple smaller capacitor units within the same trench structure. By segmenting the capacitor into multiple electrodes and insulative layers arranged in series, the design achieves higher total capacitance within the reduced area available from smaller pitch, thus resolving the contradiction between integration density and capacitance quantity
Solution Approach 2:
The patent implements a nested structure where multiple capacitor units are placed within a single trench. The electrodes and insulative layers are arranged concentrically or in stacked configurations, allowing one capacitor structure to contain multiple functional capacitor units, thereby increasing total capacitance without requiring additional trench area
Data Source
AI summary
The present disclosure relates to an integrated chip including a dielectric structure over a substrate. A first capacitor is disposed between sidewalls of the dielectric structure. The first capacitor includes a first electrode between the sidewalls of the dielectric structure and a second electrode between the sidewalls and over the first electrode. A second capacitor is disposed between the sidewalls. The second capacitor includes the second electrode and a third electrode between the sidewalls and over the second electrode. A third capacitor is disposed between the sidewalls. The third capacitor includes the third electrode and a fourth electrode between the sidewalls and over the third electrode. The first capacitor, the second capacitor, and the third capacitor are coupled in parallel by a first contact on a first side of the first capacitor and a second contact on a second side of the first capacitor.