Multilayer Via Interconnect Layout for Reliable Chip Bonding
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Solution Overview
Problem
The reliability of electronic devices is compromised due to the high likelihood of defects in vias formed during the etching process for electrical connections through multiple insulating layers, which are thick and have varying material properties.
Innovation Solution
The design includes multiple conductive layers and vias that allow for electrical connections between the conductive layers and the chip through different paths, reducing the number of insulating layers that need to be penetrated, thereby minimizing the risk of defects and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple insulating layers with large thickness and different material properties are used for electrical connection, then the insulation performance is improved, but the reliability of via formation deteriorates due to increased defect possibilities
Solution Approach 1:
The patent divides the single thick insulating layer into multiple thinner insulating layers (first insulating layer and second insulating layer). This segmentation reduces the thickness of each individual layer that needs to be etched, thereby decreasing the likelihood of defects during via formation while maintaining the overall insulation performance through the stacked structure.
Solution Approach 2:
The patent introduces a conductive layer as an intermediary between the substrate and the chip. This conductive layer provides an intermediate connection point, allowing electrical connection to be established without requiring a single via to penetrate through all insulating layers simultaneously, thus reducing the complexity and defect risk of the via formation process.
2Manufacturing precision
If multiple insulating layers are etched to form vias for electrical connection, then the electrical connection capability is improved, but the manufacturing precision deteriorates due to varying material properties
Solution Approach 1:
By segmenting the insulating structure into multiple thinner layers, each etching process operates on a reduced thickness with more uniform material properties. This improves the precision of via formation in each layer while maintaining overall connection reliability through the distributed via structure across multiple layers.
Data Source
AI summary
An electronic device including a substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a bonding structure, and a chip is provided. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first via. The second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the first via. The second insulating layer is disposed on the second conductive layer and has a second via. The bonding structure is disposed on the second insulating layer, wherein the bonding structure is electrically connected to the second conductive layer through the second via. The chip is disposed on the bonding structure.