Multi-Layer Via Structure for Etch-Resistant Reliable Interconnects
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Solution Overview
Problem
Conductive vias in semiconductor devices often extend through only one dielectric layer, limiting current carrying capability and exacerbating issues with hybrid bonding due to size differences between vias and conductive pads, especially in multi-layer structures.
Innovation Solution
Employment of multi-layer vias that extend through multiple dielectric layers, accompanied by a lateral etch casing to prevent etching damage and corrosion, enhancing current carrying capability while maintaining reliable electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-layer vias are used, then the fabrication process is simpler, but the current carrying capability is limited
Solution Approach 1:
The patent transitions from single-layer vias to multi-layer vias that extend through multiple dielectric layers, adding vertical dimensionality to the via structure. This dimensional change enables increased current carrying capability by providing larger cross-sectional area and multiple conduction paths, while the systematic fabrication process manages the associated complexity.
2Reliability
If multi-layer vias are used to improve current carrying capability, then etching damage and corrosion become more severe
Solution Approach 1:
The patent introduces lateral etch casings as intermediary protective structures surrounding the multi-layer vias. These casings act as barriers that prevent etching damage and corrosion from reaching the via structures, thereby protecting the electrical connections while enabling the use of multi-layer vias for improved current carrying capability.
Solution Approach 2:
The lateral etch casings are formed in advance before the etching process that creates the multi-layer via openings. This preliminary protective structure cushions and protects the surrounding dielectric material and via structures from harmful etching effects, preventing damage before it occurs.
3Reliability
If via size is increased to improve current carrying capability, then hybrid bonding becomes more difficult due to size mismatch with conductive pads
Solution Approach 1:
The patent uses multi-layer vias that extend through multiple dielectric layers to increase current carrying capability in the vertical dimension, while maintaining via footprint dimensions that are compatible with conductive pads for hybrid bonding. This separates the current carrying function (achieved through vertical extension) from the bonding interface function (maintained through planar dimensions).
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods to improve reliability of multi-layer vias are disclosed. An example apparatus includes: a first dielectric layer; a second dielectric layer; a metal layer between the first and second dielectric layers; a multi-layer via that extends through the first and second dielectric layers and through the metal layer; and a ring in the metal layer. The ring substantially encircles the multi-layer via.