Multi-Layer Via Interconnect Structure for Leakage and Breakdown Control
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Solution Overview
Problem
Current low-k dielectric materials used in semiconductor manufacturing are not ideal due to their dielectric constant and other characteristics, leading to increased parasitic capacitance and RC delay in signal propagation.
Innovation Solution
An interconnect structure is formed with an intermediate layer between the inter-metal dielectric and etch stop layer, having a different k-value and etch rate, resulting in vias with more vertical sidewalls and increased distance between conductive lines, reducing leakage currents and improving breakdown voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to reduce parasitic capacitance and RC delay, then signal propagation performance is improved, but material hardness and strength deteriorate making manufacturing difficult
Solution Approach 1:
The patent uses a composite dielectric structure with multiple layers having different k-values. The first dielectric layer has k1 and the second dielectric layer has k2, where k1 < k2. This composite approach allows the structure to achieve lower overall parasitic capacitance while the second layer with higher k-value provides mechanical strength and hardness, resolving the contradiction between electrical performance and mechanical properties.
Solution Approach 2:
Different regions of the dielectric structure are assigned different materials with different k-values based on local requirements. The first dielectric layer with lower k-value is placed where electrical performance is critical, while the second dielectric layer with higher k-value is placed where mechanical support is needed, optimizing both electrical and mechanical properties in their respective locations.
2Ease of manufacture
If via etching is performed through uniform dielectric layers, then manufacturing process is simple, but via sidewalls become non-vertical reducing breakdown voltage
Solution Approach 1:
The patent changes the etch rate parameter by using dielectric layers with different k-values, which inherently have different etch rates. The first dielectric layer etches at a first rate while the second dielectric layer etches at a second rate, creating self-aligned vertical via sidewalls. This parameter change resolves the contradiction by making sidewall verticality a natural consequence of the material properties rather than a result of complex process control.
3Productivity
If distance between conductive lines is reduced to increase density, then device integration is improved, but leakage currents increase reducing reliability
Solution Approach 1:
The patent employs a composite dielectric structure where the first dielectric layer with lower k-value is positioned between adjacent conductive lines to minimize capacitive coupling and leakage currents. The second dielectric layer with higher k-value provides mechanical support. This composite approach enables closer spacing of conductive lines while maintaining low leakage, thus resolving the contradiction between integration density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved vertical profile of vias reduces leakage currents and increases breakdown voltages, enhancing device reliability and processing window for electrical testing.
Implementation Method 1
a via that is formed has more vertical sidewalls in the intermediate layer than it does in the IMD
Data Source
AI summary
An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.