Multi-Layer Via Structure for Vertical Profiles in Low-k Interconnects
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Solution Overview
Problem
Current low-k dielectric materials used in semiconductor manufacturing are not ideal due to their dielectric constant and other characteristics, leading to issues with parasitic capacitance and RC delay in signal propagation.
Innovation Solution
An interconnect structure with an intermediate layer having a different k-value and etch rate than the IMD, resulting in vias with more vertical sidewalls, increasing the distance between vias and adjacent conductive lines, thereby reducing leakage currents and improving breakdown voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to reduce parasitic capacitance and RC delay, then signal propagation performance is improved, but material hardness and strength deteriorate making manufacturing difficult
Solution Approach 1:
The patent uses a composite dielectric structure combining low-k material (for reduced RC delay) with a harder intermediate layer material (for manufacturing support). This composite approach allows the system to benefit from both the low-k material's electrical performance and the intermediate layer's mechanical strength, resolving the contradiction between signal propagation performance and material hardness.
Solution Approach 2:
The intermediate layer acts as a mediator between the low-k dielectric material and the manufacturing process. By introducing this intermediate layer with different etch selectivity, the patent enables better via profile control and manufacturing precision without compromising the low-k material's electrical properties, thus resolving the contradiction between reliability and ease of manufacture.
2Ease of manufacture
If via openings are etched through low-k dielectric layers, then interconnect functionality is achieved, but via profile control deteriorates due to material softness and similar etch rates
Solution Approach 1:
The intermediate layer serves as an intermediary with distinct etch selectivity compared to the low-k dielectric material. This difference in etch rates allows the via walls to be formed with better verticality during the etching process, improving manufacturing precision without sacrificing ease of manufacture.
Solution Approach 2:
The patent applies local quality by creating an intermediate layer with specific properties (different k-value and etch rate) only in the region where via formation occurs. This localized modification improves via profile control precisely where needed, while leaving the rest of the low-k dielectric structure intact for its electrical function.
3Reliability
If via distance to conductive lines is increased to reduce leakage currents, then device reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the problem of leakage current control from the geometric design (via spacing) and transfers it to the material design (intermediate layer with different etch selectivity). By etching the intermediate layer at a different rate, the via profile naturally achieves better spacing control, reducing leakage without requiring increased physical distance or additional structural elements.
Data Source
AI summary
An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.