Multi-Layer Waveguide Delay Structure for High-Speed Signal Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing receiver circuitry faces challenges in accurately sampling high-speed signals due to size constraints, as increasing parasitic impedance without extending waveguides is difficult, necessitating innovative methods to enhance parasitic inductance and capacitance.
Innovation Solution
Structuring waveguides across multiple layers with overlapping surface areas and using a non-conducting layer to separate them, thereby increasing parasitic capacitance and reducing propagation speed, allowing for shorter waveguide lengths and enhanced delay durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If waveguide length is increased to increase parasitic impedance, then delay duration is improved, but device area and package size increase
Solution Approach 1:
The patent transitions from planar waveguide routing to three-dimensional multi-layer routing. Waveguides are routed across different metal layers (e.g., from metal layer 4 to metal layer 1) and connected via vias, utilizing the vertical dimension to achieve longer effective waveguide length without increasing the planar footprint. This allows the waveguide to traverse through the package volume rather than being constrained to a two-dimensional path.
Solution Approach 2:
The patent embeds multiple waveguide segments across different layers within a compact vertical stack. The waveguide path is nested through multiple metal layers separated by dielectric layers, with each layer contributing a segment of the total waveguide length. This nested multi-layer structure achieves extended delay duration while maintaining a compact overall device footprint.
2Measurement precision
If waveguide length is increased to improve delay duration, then sampling accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the continuous waveguide into discrete segments routed on different metal layers, connected by vias. Each metal layer contains a segment of the waveguide, and the vias provide vertical interconnections between layers. This segmentation allows the waveguide to achieve extended length through standard multi-layer PCB fabrication processes, avoiding the need for a single long waveguide trace that would be difficult to manufacture and route.
3Duration of action of moving object
If parasitic capacitance is increased to reduce propagation speed, then delay duration is improved, but waveguide length must be increased
Solution Approach 1:
The patent increases parasitic capacitance by routing waveguides across multiple layers with vertical separation. The capacitance arises from the electric field coupling between waveguide segments on different layers through the dielectric material. This three-dimensional arrangement provides additional capacitance pathways without requiring proportionally longer waveguide traces, as the vertical field coupling contributes to the total parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate sampling of high-speed signals by decreasing waveguide length and footprint, facilitating efficient signal sequencing and sampling across multiple analog-to-digital converters.
Implementation Method 1
increasing parasitic capacitance and reducing propagation speed
Data Source
AI summary
An example apparatus includes: a first metal layer including: a first delay line having a surface area; and a second metal layer including: a second delay line having a surface area overlapping the surface area of the first delay line; and an insulating layer coupled between the first metal layer and the second metal layer.