Multilayer Winding Inductor with Nested Interconnects
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Solution Overview
Problem
Conventional on-chip inductors, such as planar spiral and solenoid structures, face challenges in reducing size while maintaining a high quality factor (Q value), which limits integration and increases manufacturing costs due to parasitic effects and series resistance.
Innovation Solution
A multilayer winding inductor with a multi-level interconnect structure is developed, featuring overlapping looped conductive traces connected in parallel and series, embedded in an insulating layer on a semiconductor substrate, to reduce series resistance and maintain the Q value while minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar spiral inductor structure is used, then the inductor can be formed with simple manufacturing process, but the inductor occupies larger chip area and has larger size
Solution Approach 1:
The patent transitions from a planar two-dimensional spiral structure to a three-dimensional multilayer winding structure. Multiple conductive traces are stacked in different layers (first, second, and third conductive layers) with vertical interconnects, effectively utilizing the third dimension to reduce the horizontal footprint on the chip while maintaining inductance characteristics.
Solution Approach 2:
The patent implements nested winding patterns where conductive traces in upper layers are positioned to overlap and interleave with traces in lower layers. The second conductive trace winds around and overlaps with portions of the first conductive trace, creating a compact nested configuration that maximizes space utilization and reduces overall inductor size.
2Area of stationary object
If the solenoid structure is used to decrease inductor size, then the chip area is reduced, but the series resistance increases due to thinner conductive traces
Solution Approach 1:
The patent combines multiple conductive traces from different layers in parallel to form the inductor winding. The first, second, and third conductive traces are electrically connected through conductive plugs to create parallel current paths, which reduces the overall series resistance while maintaining the compact three-dimensional structure.
Solution Approach 2:
The patent employs composite interconnect structures combining horizontal conductive traces in multiple layers with vertical conductive plugs. This composite architecture allows current to flow through multiple parallel paths, reducing resistance while maintaining the compact solenoid-like geometry.
3Area of stationary object
If the spiral conductive trace interval is reduced to decrease inductor size, then the inductor occupies smaller area, but the manufacturing precision requirements increase
Solution Approach 1:
By moving from a planar spiral to a multilayer configuration, the patent reduces the horizontal spacing requirements between traces. The vertical separation between conductive layers provides additional design freedom, allowing larger horizontal trace intervals while achieving compact overall dimensions through the third dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayer winding inductor achieves reduced series resistance, allowing for smaller size and higher integration with preserved Q value, enhancing device performance and integration density.
Implementation Method 1
utilize the inductance induced by the coil
Data Source
AI summary
A multilayer winding inductor. The inductor at least includes multi-level interconnect and single-level interconnect structures. The multi-level interconnect structure includes a plurality of conductive plugs and a plurality of looped conductive traces overlapping and separated from each other. Each looped conductive trace has a gap to define first and second ends and at least two conductive plugs disposed between the neighboring looped conductive traces. The single-level interconnect structure is located over the multi-level interconnect structure, comprising an uppermost looped conductive trace and a second conductive plug. The uppermost looped conductive trace has a gap to define first and second ends, and the second conductive plug is disposed between the second end of the uppermost looped conductive trace and the first end of the looped conductive trace adjacent thereto, thereby electrically connecting the multi-level and single-level interconnect structures.