Multi-Layer Wire Bond Pad Layout for Tight-Pitch IC Packaging
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Solution Overview
Problem
The increasing complexity of integrated circuits and the use of multiple IC dice in a single device lead to challenges in wire bond pad pitch, manufacturability, and parasitic effects due to tight wire bond pad pitches, which are difficult to achieve with current technologies.
Innovation Solution
A multi-layer substrate with an open area that exposes wire bond pads on an inner layer, allowing for tighter wire bond pad pitches without the precision challenges of current methods, and reduces parasitic effects by separating wire traces across different layers with dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If tight wire bond pad pitches are used to increase the number of wire bond pads, then the quantity of wire bond pads increases, but manufacturing precision deteriorates due to precision challenges in current technologies
Solution Approach 1:
The patent transitions from a two-dimensional arrangement of wire bond pads on a single substrate layer to a three-dimensional configuration by placing wire bond pads on multiple layers (first layer and second layer). This dimensional change allows the system to accommodate a greater number of wire bond pads without reducing the pitch on any single layer, thereby maintaining manufacturing precision while increasing the total quantity of wire bond pads.
2Productivity
If tight wire bond pad pitches are used to increase substrate capacity, then substrate usage efficiency improves, but device complexity increases due to parasitic effects
Solution Approach 1:
By distributing wire bond pads across multiple layers, the patent reduces the density of wire traces on any single layer. This multi-layer configuration separates wire traces in the vertical dimension, reducing electromagnetic interference and parasitic effects between adjacent traces. Consequently, the system achieves improved substrate usage efficiency without significantly increasing device complexity related to parasitic effects.
Solution Approach 2:
The patent segments the wire bond pad arrangement into multiple layers, with each layer containing a subset of the total wire bond pads. This segmentation allows wire traces on different layers to be spatially separated, reducing mutual interference and parasitic coupling. The segmentation strategy enables higher overall substrate utilization while maintaining manageable levels of parasitic effects through layer-based isolation.
3Quantity of substance
If more wire bond pads are placed on a single layer, then the number of wire bond pads increases, but manufacturing difficulty increases due to etching challenges
Solution Approach 1:
The patent resolves the etching difficulty by distributing wire bond pads across multiple layers rather than concentrating them on a single layer. This multi-layer approach reduces the linear density of wire traces that must be etched on any given layer, making the etching process more manageable and precise. The total number of wire bond pads increases through vertical stacking of layers, while each individual layer maintains etching feasibility.
Data Source
AI summary
An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.