Multi-Layer Wiring Board Signal Routing for Noise Reduction
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Solution Overview
Problem
Current electronic assemblies, particularly those using daisy chain and T-type topologies for signal wiring between a central processing unit (CPU) and dual in-line memory modules (DIMM), suffer from increased coupling noise and signal quality issues due to long wiring distances and the need for additional rewound signal wiring, which affects high-speed signal transmission.
Innovation Solution
The electronic assembly incorporates a wiring board with multiple patterned conductive layers and conductive holes, allowing the conductive path to extend through different layers to reduce coupling noise and improve signal quality by shortening wiring distances and minimizing the number of through holes, thereby implementing a more flexible and efficient routing topology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If signal wiring uses traditional single-layer routing with long wiring distances, then device complexity is reduced, but coupling noise increases and signal quality deteriorates
Solution Approach 1:
The patent transitions from single-layer planar routing to multi-layer three-dimensional routing. Conductive paths are distributed across multiple patterned conductive layers (first, second, third layers) with conductive holes connecting them, creating a vertical dimension for signal transmission. This dimensional expansion shortens horizontal wiring distances and reduces coupling noise between adjacent signals.
Solution Approach 2:
The conductive path is segmented into multiple sections across different layers. Instead of a single continuous trace, the signal path is divided into segments on the first patterned conductive layer, second patterned conductive layer, and third patterned conductive layer, connected by conductive holes. This segmentation allows optimization of each segment's routing to minimize noise coupling.
2Reliability
If wiring distance is shortened to improve signal quality, then signal transmission performance improves, but the number of conductive layers and through holes increases
Solution Approach 1:
By utilizing the vertical dimension through multiple conductive layers, the patent achieves shorter effective signal paths. Signals that would require long horizontal traces on a single layer are instead routed through stacked layers connected by vertical conductive holes, dramatically reducing the overall path length and improving signal quality.
Solution Approach 2:
The patent changes the routing parameters by introducing multiple conductive layers at different vertical positions. This parameter change allows the system to trade structural complexity (more layers) for performance improvement (shorter effective wiring distance and reduced noise), optimizing the signal transmission characteristics for high-speed applications.
3Adaptability or versatility
If traditional single-layer routing is used, then manufacturing simplicity is maintained, but wiring flexibility and routing options are limited
Solution Approach 1:
The multi-layer structure provides additional routing dimensions and pathways. Designers can route signals through different layer combinations to avoid obstacles, reduce interference, and achieve optimal signal paths that would be impossible on a single layer, greatly enhancing wiring flexibility and routing adaptability.
Solution Approach 2:
The multiple patterned conductive layers serve multiple functions: they provide alternative routing paths for different signals, enable crossing of signal traces without interference, provide shielding layers for noise reduction, and offer redundant pathways for signal integrity. This multi-functionality justifies the increased manufacturing complexity.
Data Source
AI summary
An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.