Multilayer Wiring Substrate Correction for Pattern Alignment
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Solution Overview
Problem
Existing methods for manufacturing multilayer wiring substrates face challenges in accurately forming conductor patterns due to dimensional deviations caused by substrate shrinkage and warpage, leading to variations in conductor layer dimensions and potential misalignment of patterns, which can result in inadequate precision and increased manufacturing costs.
Innovation Solution
A method that involves forming a resist layer with a mask pattern, performing a first correction to align the pattern position and a second correction to adjust the pattern shape, and selectively applying these corrections to specific layers to minimize positional deviations and dimensional variations across multiple conductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dimensional correction is applied to all conductor layers, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies dimensional correction selectively only to the first conductor layer instead of all conductor layers. This local quality approach maintains high manufacturing precision where it is most critical (at the base layer that establishes the reference framework) while avoiding unnecessary complexity in subsequent layers, thereby resolving the contradiction between precision and device complexity
Solution Approach 2:
The patent performs dimensional correction in advance during the formation of the first conductor layer, establishing accurate reference patterns before subsequent layers are formed. This preliminary action ensures that all subsequent layers can be aligned to this corrected reference, achieving overall high precision without requiring correction at every layer
2Manufacturing precision
If dimensional correction is applied to all conductor layers, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements correction only for the first conductor layer, applying the corrective action locally where it provides maximum benefit. This reduces the total number of correction operations required, directly lowering manufacturing costs while maintaining the necessary precision for the overall multilayer structure
Solution Approach 2:
By performing the dimensional correction once at the beginning during first conductor layer formation, the patent eliminates the need for repeated correction operations in subsequent layers. This preliminary correction establishes a stable reference framework that guides all subsequent layer formation, reducing total process steps and associated costs
3Ease of manufacture
If no dimensional correction is applied, then manufacturing cost is reduced, but manufacturing precision deteriorates due to substrate shrinkage and warpage
Solution Approach 1:
The patent performs dimensional correction as a preliminary step during the formation of the first conductor layer, compensating for substrate shrinkage and warpage effects before they propagate to subsequent layers. This early correction establishes accurate reference patterns that guide all subsequent layer formation, ensuring high precision without requiring correction at every layer
Solution Approach 2:
The patent segments the correction process by applying it only to the critical first conductor layer that serves as the reference framework, rather than uniformly applying correction to all layers. This segmentation maintains manufacturing precision where it is most needed while avoiding unnecessary complexity and cost in subsequent layers
Data Source
AI summary
A method for manufacturing a multilayer wiring substrate includes forming a resist layer having mask pattern, forming a conductor layer having conductor pattern using the resist layer, removing the resist layer, forming an insulating layer on the conductor layer such that the insulating layer is laminated on the conductor layer, forming a subsequent resist layer having mask pattern such that the subsequent resist layer is formed on the insulating layer, and forming a subsequent conductor layer having conductor pattern using the subsequent resist layer. The forming of the resist layer includes conducting first correction in which formation position of entire mask pattern of the resist layer is corrected with respect to reference position, and conducting second correction in which shape of the mask pattern of the resist layer is corrected with respect to reference shape, and the forming of the subsequent resist layer does not include conducting the second correction.