Multilayer Wiring Substrate with Segmented Insulating Layers
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Solution Overview
Problem
The challenge is to reduce the mounting height and outer dimensions of semiconductor devices while maintaining the strength of the wiring substrate, as the use of prepreg materials with glass cloth enhances strength but complicates the formation of narrow wiring patterns due to processing accuracy issues and increased warpage caused by thermal expansion differences between the substrate and chip materials.
Innovation Solution
A multilayer wiring substrate configuration using a core material with prepreg layers containing glass cloth and additional insulating layers with reduced fiber content, allowing for thinner seed layers and smaller via diameters, and employing electroless plating for seed layer formation to reduce wiring pattern width and pitch, while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If prepreg materials with glass cloth are used to enhance wiring substrate strength, then substrate strength is improved, but manufacturing precision deteriorates due to processing accuracy issues and increased warpage
Solution Approach 1:
The patent divides the insulating layer into two distinct types: a first insulating layer made of prepreg material containing glass cloth for strength, and a second insulating layer made of resin without glass cloth for precision processing. This segmentation allows each layer to fulfill its specific function without compromise.
Solution Approach 2:
Different regions of the insulating layer are assigned different material properties: the first insulating layer (with glass cloth) provides mechanical strength where needed, while the second insulating layer (resin-based) enables high-precision wiring pattern formation in areas requiring fine processing accuracy.
2Strength
If prepreg materials with glass cloth are used to enhance wiring substrate strength, then substrate strength is improved, but device height increases
Solution Approach 1:
The patent segments the insulating layer into a first insulating layer (prepreg with glass cloth) and a second insulating layer (resin without glass cloth), allowing the overall height to be controlled by optimizing the thickness distribution between the two layers while maintaining necessary strength.
Solution Approach 2:
The patent changes the material composition parameter of the insulating layer by introducing a second resin-based layer with reduced fiber content, which has different mechanical and processing properties that enable both strength maintenance and height reduction.
3Manufacturing precision
If electroless plating is used for seed layer formation to reduce wiring pattern width and pitch, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies electroless plating to form a seed layer on the second insulating layer before wiring pattern formation. This preliminary action creates a uniform base that enables subsequent precise pattern formation with reduced width and pitch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of semiconductor device height and size while ensuring the strength and reliability of the wiring substrate, allowing for efficient routing of current paths and effective mounting on motherboards despite thermal expansion differences.
Implementation Method 1
employing electroless plating for seed layer formation to reduce wiring pattern width and pitch
Implementation Method 2
applying a laser beam through the surface copper foil opening 23 to form a hole 16 for via hole
Implementation Method 3
increased warpage caused by thermal expansion differences between the substrate and chip materials
Data Source
AI summary
A multilayer wiring substrate has an upper surface with multiple bonding leads and a lower surface with multiple lands. Multiple wiring layers and insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper and lower surface sides of the core material. The third insulating layers are formed on the upper and lower surface sides of the core material with the second insulating layers in-between. The uppermost and lowermost wiring layers are formed over the third insulating layers.