Multilayered Power Line Network for Semiconductor Chips
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Solution Overview
Problem
Semiconductor chip power line networks, particularly those supplying power to circuit blocks with high current consumption, face challenges in maintaining low resistivity due to long wire lengths, which affects the efficiency of data sense amplifiers and decoders.
Innovation Solution
The implementation of a multi-layered wiring structure with alternately arrayed power supply patterns and increased via conductors connecting these patterns across layers, reducing resistance and enabling higher current supply to data sense amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-layer power line network is used, then the device complexity is low, but the resistance is high due to long wire lengths
Solution Approach 1:
The patent transitions from a single-layer power line network to a multilayered power line network, adding vertical dimensionality to the power distribution structure. This allows power to be supplied through multiple layers simultaneously, reducing the effective path length and resistance while maintaining manageable complexity through systematic layer organization.
Solution Approach 2:
The power line network is segmented into multiple independent layers, each carrying a portion of the total power current. This segmentation distributes the power supply function across multiple parallel paths, reducing the resistance of any single path and improving overall power delivery efficiency to high current consumption blocks.
2Reliability
If wire length is reduced, then resistance decreases, but the area covered by power lines must be increased
Solution Approach 1:
By utilizing multiple vertical layers, the patent reduces the horizontal wire length required within each layer while maintaining comprehensive area coverage. The multilayer structure allows power lines to serve multiple regions through vertical stacking, effectively reducing the total trace length needed compared to a single expansive layer.
Data Source
AI summary
Disclosed herein is an apparatus that includes a first wiring layer including a first power line extending in a first direction, a second wiring layer including second and third power lines extending in a second direction, a third wiring layer including power electrode patterns arranged in the second direction, and a fourth wiring layer including a fourth power line extending in the second direction. The first and second power lines are connected by a first via electrode. The first and third power lines are connected by a second via electrode. The second power line and each of the power electrode patterns are connected by a third via electrode. The third power line and each of the power electrode patterns are connected by a fourth via electrode. The fourth power line and each of the power electrode patterns are connected by a fifth via electrode.